Philips ISP1181A User Manual

ISP1181A

Full-speed Universal Serial Bus peripheral controller

Rev. 05 — 08 December 2004 Product data

1. General description

The ISP1181A is a Universal Serial Bus (USB) peripheral controller that complies with

UniversalSerial Bus Speciﬁcation Rev. 2.0

(12 Mbit/s). It provides full-speed USB communication capacity to microcontroller or microprocessor-based systems. The ISP1181A communicates with the system’s microcontroller or microprocessor through a high-speed general-purpose parallel interface.

The ISP1181A supports fully autonomous, multi-conﬁgurable Direct Memory Access (DMA) operation.

The modular approach to implementing a USB peripheral controller allows the designer to select the optimum system microcontrollerfrom the wide variety available. The ability to reuse existing architecture and ﬁrmware investments shortens development time, eliminates risks and reduces costs. The result is fast and efﬁcient development of the most cost-effective USB peripheral solution.

, supporting data transferat full-speed

2. Features

The ISP1181A is ideally suited forapplication in many personal computer peripherals such as printers, communication devices, scanners, external mass storage (Zip drive) devices and digital still cameras. It offers an immediate cost reduction for applications that currently use SCSI implementations.

■ Complies with

speciﬁcations

■ Supports data transfer at full-speed (12 Mbit/s)

■ High performance USB peripheral controller with integrated Serial Interface

Engine (SIE), FIFO memory, transceiver and 3.3 V voltage regulator

■ High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface

■ Fully autonomous and multi-conﬁguration DMA operation

■ Up to 14 programmable USB endpoints with 2 ﬁxed control IN/OUT endpoints

■ Integrated physical 2462 bytes of multi-conﬁguration FIFO memory

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer

■ Seamless interface with most microcontrollers/microprocessors

■ Bus-powered capability with low power consumption and low ‘suspend’ current

■ 6 MHz crystal oscillator input with integrated PLL for low EMI

■ Controllable LazyClock (100 kHz ± 50 %) output during ‘suspend’

■ Software controlled connection to the USB bus (SoftConnect™)

■ Good USB connection indicator that blinks with trafﬁc (GoodLink™)

Universal Serial Bus Speciﬁcation Rev.2.0

and most Device Class

Philips Semiconductors

■ Clock output with programmable frequency (up to 48 MHz)

■ Complies with the ACPI™, OnNow™ and USB power management requirements

■ Internal power-on and low-voltage reset circuit, with possibility of a software reset

■ Operation over the extended USB bus voltage range (4.0 V to 5.5 V) with 5 V

■ Operating temperature range −40 °Cto+85 °C

■ Full-scan design with high fault coverage

■ Available in TSSOP48 and HVQFN48 packages.

3. Applications

■ Personal Digital Assistant (PDA)

■ Digital camera

■ Communication device, for example:

■ Mass storage device, for example:

■ Printer

■ Scanner.

ISP1181A

Full-speed USB peripheral controller

tolerant I/O pads

◆ Router

◆ Modem

◆ Zip drive

4. Ordering information

Table 1: Ordering information

Type number Package

Name Description Version

ISP1181ADGG TSSOP48 Plastic thin shrink small outline package; 48leads; body width 6.1 mm SOT362-1 ISP1181ABS HVQFN48 Plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 7 × 7 × 0.85 mm

SOT619-2

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5. Block diagram

Philips Semiconductors

to/from USB

D−

D+

3.3 V

1.5 kΩ

ANALOG

Tx/Rx

RESET

POWER-ON

RESET

VOLTAGE

REGULATOR

REGGND

GL CLKOUT

BUS

sense input XTAL1

74847

HUB

GoodLink

SoftConnect

internal reset

3.3 V

reg(3.3)

6 MHz

XTAL2to LED

PLL

OSCILLATOR

BIT CLOCK

RECOVERY

PHILIPS

SIE

3.3 V

SUSPEND8WAKEUP

MHz

GND37V

PROGR. DIVIDER

MEMORY

MANAGEMENT

UNIT

INTEGRATED

RAM

INTERNAL

SUPPLY

25, 36, 46

CC(3.3)

DREQ

EOT, DACK

DMA

HANDLER

MICRO

CONTROLLER

HANDLER

ENDPOINT

HANDLER

I/O PIN

SUPPLY

ref

2 10, 12

BUS

INTERFACE

ISP1181A

17 18

38, 35 to 27,

24 to 19

43 to 39

004aaa020

to/from

microcontroller

BUS_CONF0 BUS_CONF1

AD0,

DATA1 to DATA9, DATA10 to DATA15

CS, ALE, WR, RD, A0

INT

Full-speed USB peripheral controller

ISP1181A

Fig 1. Block diagram.

Philips Semiconductors

6. Pinning information

6.1 Pinning

REGGND

reg(3.3)

D− D+

BUS

WAKEUP

SUSPEND

EOT

DREQ

DACK

TEST1

TEST2

INT

TEST3

BUS_CONF0 BUS_CONF1

DATA15 DATA14 DATA13 DATA12 DATA11 DATA10

1 2 3 4 5 6 7 8

9 10 11 12

ISP1181ADGG

13 14 15 16 17 18 19 20 21 22 23 24

ISP1181A

Full-speed USB peripheral controller

XTAL1

XTAL2

GND

CLKOUT

RESET

ALE

40 39

AD0 V

CC(3.3)

GND

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9 V

ref

GND

004aaa019

Fig 2. Pin conﬁguration TSSOP48.

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BUS_CONF0

TEST3

INT TEST2 TEST1

DACK

DREQ

EOT

SUSPEND

WAKEUP

BUS

Bottom view

12 11 10

9 8 7 6 5 4 3 2 1

DATA14

DATA15

BUS_CONF1 13

DATA13

ISP1181ABS

464845

47 D−

D+

reg(3.3)

REGGND

ISP1181A

Full-speed USB peripheral controller

ref

DATA10

GND

DATA11

DATA12

181620

XTAL1

GND

XTAL2

CLKOUT

DATA8

DATA9 222321

393840

RESET

DATA7 24

25 26 27 28 29 30 31 32 33 34 35 36

ALE

DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 GND V

CC(3.3)

AD0 A0 RD WR

004aaa021

Fig 3. Pin conﬁguration HVQFN48.

6.2 Pin description

Table 2: Pin description

reg(3.3)

BUS

[1]

Pin Type Description TSSOP48 HVQFN48

1 44 - supply voltage (3.3 V or 5.0 V)

3 46 - regulated supply voltage (3.3 V ± 10 %)

from internal regulator; used to connect decoupling capacitor andpull-upresistoron D+ line;

Remark: Cannotbeusedto supply external devices.

61IV

sensing input

BUS

8 mA); the LED is default ON, blinks OFF upon USB trafﬁc; to connect an LED use a series resistor of 470 Ω (V 330 Ω (V

= 3.3 V)

LOW to HIGH); generates a remote wake-up from ‘suspend’ state

used as power switch control output (active LOW) for powered-off application

Symbol

V REGGND 2 45 - voltage regulator ground supply V

D− 4 47 AI/O USB D− connection (analog) D+ 5 48 AI/O USB D+ connection (analog) V GL 7 2 O GoodLink LED indicator output (open-drain,

WAKEUP 8 3 I wake-up input (edge triggered,

SUSPEND 9 4 O ‘suspend’ state indicator output (4 mA);

= 5.0 V) or

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ISP1181A

Full-speed USB peripheral controller

Table 2: Pin description

Symbol

[1]

Pin Type Description

…continued

TSSOP48 HVQFN48

EOT 10 5 I End-Of-Transfer input (programmable

polarity, see Table 21); used by the DMA controller to force the end of a DMA transfer to the ISP1181A

DREQ 11 6 O DMA request output (4 mA; programmable

polarity, see Table 21); signals to the DMA controller that the ISP1181A wants to start a DMA transfer

DACK 12 7 I DMA acknowledge input (programmable

polarity, see Table 21); used by the DMA controller to signal the start of a DMA transfer requested by the ISP1181A

TEST1 13 8 I test input; this pin must be connected to

via an external 10 kΩ resistor

TEST2 14 9 I test input; this pin must be connected to

via an external 10 kΩ resistor

INT 15 10 O interrupt output; programmable polarity

(active HIGH or LOW) and signalling (level or pulse); see Table 21

TEST3 16 11 O test output; this pin is used for test

purposes only BUS_CONF0 17 12 I bus conﬁguration selector; see Table 3 BUS_CONF1 18 13 I bus conﬁguration selector; see Table 3 DATA15 19 14 I/O bit 15 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA14 20 15 I/O bit 14 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA13 21 16 I/O bit 13 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA12 22 17 I/O bit 12 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA11 23 18 I/O bit 11 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA10 24 19 I/O bit 10 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) GND 25 20 - ground supply V

ref

26 21 - I/O pin reference voltage (3.3 V); no

connection if V

= 5.0 V

DATA9 27 22 I/O bit9 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA8 28 23 I/O bit8 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA7 29 24 I/O bit7 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA6 30 25 I/O bit6 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA)

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ISP1181A

Full-speed USB peripheral controller

Table 2: Pin description

Symbol

[1]

Pin Type Description

…continued

TSSOP48 HVQFN48

DATA5 31 26 I/O bit5 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA4 32 27 I/O bit4 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA3 33 28 I/O bit3 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA2 34 29 I/O bit2 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) DATA1 35 30 I/O bit1 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA) GND 36 31 - ground supply V

CC(3.3)

37 32 - supply voltage (3.0 V to 3.6 V); leave this

pin unconnected when using V

= 5.0 V

AD0 38 33 I/O multiplexed bidirectional address and data

line; represents address A0 or bit 0 of

D[15:0] in conjunction with input ALE;

level-sensitive input or slew-rate controlled

output (4 mA)

Address phase: a HIGH-to-LOW transition

on input ALE latches the level on this pin as

address A0 (1 = command, 0 = data)

Data phase: during reading this pin outputs

bit D[0]; during writing the levelonthispinis

latched as bit D[0] A0 39 34 I address input;selectscommand(A0 = 1) or

data (A0 = 0); in a multiplexed address/data

bus conﬁguration this pin is not used and

must be tied LOW (connect to GND) RD 40 35 I read strobe input WR 41 36 I write strobe input ALE 42 37 I address latch enable input; a HIGH-to-LOW

transition latches the level on pin AD0 as

address information in a multiplexed

address/data bus conﬁguration; must be

tied LOW (connect to GND) for a separate

address/data bus conﬁguration CS 43 38 I chip select input RESET 44 39 I reset input (Schmitt trigger); a LOW level

produces an asynchronous reset; connect

for power-on reset (internal POR

to V

circuit) CLKOUT 45 40 O programmable clock output (2 mA)

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ISP1181A

Full-speed USB peripheral controller

Table 2: Pin description

Symbol

GND 46 41 - ground supply XTAL2 47 42 O crystal oscillator output (6 MHz); connect a

XTAL1 48 43 I crystal oscillator input (6 MHz); connect a

[1] Symbol names with an overscore (for example, NAME) represent active LOW signals.

[1]

Pin Type Description TSSOP48 HVQFN48

…continued

fundamental parallel-resonantcrystal; leave

this pin open when using an external clock

source on pin XTAL1

fundamental parallel-resonant crystal or an

external clock source (leave pin XTAL2

unconnected)

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7. Functional description

The ISP1181A is a full-speed USB peripheral controller with up to 14 conﬁgurable endpoints. It has a fast general-purpose parallel interface for communication with many types of microcontrollers or microprocessors. It supports different bus conﬁgurations (see Table 3) and local DMA transfers of up to 16 bytes per cycle. The block diagram is given in Figure 1.

The ISP1181A has 2462 bytes of internal FIFO memory, which is shared among the enabled USB endpoints. The type and FIFO size of each endpoint can be individually conﬁgured, depending on the required packet size. Isochronous and bulk endpoints are double-buffered for increased data throughput.

The ISP1181A requires a single supply voltage of 3.3 Vor 5.0 V and has an internal

3.3 V voltage regulator for powering the analog USB transceiver. It supports bus-powered operation.

The ISP1181A operates on a 6 MHz oscillator frequency. A programmable clock output is available up to 48 MHz. During ‘suspend’ state the 100 kHz ± 50 % LazyClock frequency can be output.

ISP1181A

Full-speed USB peripheral controller

7.1 Analog transceiver

The transceiver is compliant with the

speed)

resistors.

. It interfaces directly with the USB cable through external termination

Universal Serial Bus Speciﬁcation Rev. 2.0 (full

7.2 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no ﬁrmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de-)stufﬁng, CRC checking/generation, Packet IDentiﬁer (PID) veriﬁcation/generation, address recognition, handshake evaluation/generation.

7.3 Memory Management Unit (MMU) and integrated RAM

The MMU and the integrated RAM provide the conversion between the USB speed (12 Mbit/s bursts) and the parallel interface to the microcontroller (max. 12 Mbyte/s). This allows the microcontroller to read and write USB packets at its own speed.

7.4 SoftConnect

The connection to the USB is accomplished by bringing D+ (for full-speed USB peripherals) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1181A, the 1.5 kΩ pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established by a command sent from the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establishconnection with the USB. Reinitialization of the USB connection can also be performed without disconnecting the cable.

The ISP1181A will check for USB V established. V

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sensing is provided through pin V

BUS

availability before the connection can be

BUS

Philips Semiconductors

BUS

Without V With V there is noise on the (D+, D-) lines, it is not taken into account. This ensures that the peripheral remains in the suspend state.

Remark: Note that the tolerance of the internal resistors is 25 %. This is higher than the 5 % tolerance speciﬁed by the USB speciﬁcation. However, the overall voltage speciﬁcation for the connection can still be met with a good margin. The decision to make use of this feature lies with the USB equipment designer.

7.5 GoodLink

Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration, the LED indicator will blink on momentarily. When the ISP1181A has been successfully enumerated (the peripheral address is set), the LED indicator will remain permanently on. Upon each successful packettransfer(with ACK) to and from the ISP1181A, the LED will blink off for 100 ms. During ‘suspend’ state, the LED will remain off.

Full-speed USB peripheral controller

sensing prevents the peripheral from wake-up when V

sensing, any activity or noise on (D+, D-) might wake up the peripheral.

BUS

sensing, (D+, D-) is decoupled when no V

BUS

is present. Therefore, even if

BUS

ISP1181A

is not present.

BUS

This feature provides a user-friendly indication of the status of the USB peripheral, the connected hub,and the USB trafﬁc. It is a useful ﬁeld diagnostics tool forisolating faulty equipment. It can therefore help to reduce ﬁeld support and hotline overhead.

7.6 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4 times over-sampling principle. It is able to track jitter and frequency drift as speciﬁed by the

USB Speciﬁcation Rev. 2.0

7.7 Voltage regulator

A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver and internal logic. This voltage is availableat pin V

to supply an external 1.5 kΩ

reg(3.3)

pull-up resistor on the D+ line. Alternatively, the ISP1181A provides SoftConnect technology via an integrated 1.5 kΩ pull-up resistor (see Section 7.4).

7.8 PLL clock multiplier

A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL.

7.9 Parallel I/O (PIO) and Direct Memory Access (DMA) interface

A generic PIO interface is deﬁned for speed and ease-of-use. It also allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1181A appears as a memory device with an 8/16-bit data bus and a 1-bit address line. The ISP1181A supports both multiplexed and non-multiplexed address and data buses.

The ISP1181A can also be conﬁgured as a DMA slave device to allow more efﬁcient data transfer. One of the 14 endpoint FIFOs may directly transfer data to/from the local shared memory. The DMA interface can be conﬁgured independently from the PIO interface.

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ISP1181A

Full-speed USB peripheral controller

8. Modes of operation

The ISP1181A has fourbusconﬁguration modes, selected via pins BUS_CONF1 and BUS_CONF0:

Mode 0 16-bit I/O port shared with 16-bit DMA port Mode 1 reserved Mode 2 8-bit I/O port shared with 8-bit DMA port Mode 3 reserved.

The bus conﬁgurations foreach of these modes are given in Table 3. Typical interface circuits for each mode are given in Section 21.1.

Table 3: Bus conﬁguration modes

Mode BUS_CONF[1:0] PIO width DMA width Description

DMAWD = 0 DMAWD = 1

0 0 0 D[15:1], AD0 - D[15:1], AD0 multiplexed address/data on pin AD0;

bus is shared by 16-bit I/O port and

16-bit DMA port 1 0 1 reserved reserved reserved reserved 2 1 0 D[7:1], AD0 D[7:1], AD0 - multiplexed address/data on pin AD0;

bus is shared by 8-bit I/O port and 8-bit

DMA port 3 1 1 reserved reserved reserved reserved

9. Endpoint descriptions

Each USB peripheral is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication ﬂow between the host and the peripheral. At design time each endpoint is assigned a unique number (endpoint identiﬁer, see Table 4). The combination of the peripheral address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced.

The ISP1181A has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 conﬁgurable endpoints, which can be individually deﬁned as interrupt/bulk/isochronous, IN or OUT. Each enabled endpoint has an associated FIFO, which can be accessed either via the parallel I/O interface or via DMA.

9.1 Endpoint access

Table 4 lists the endpoint access modes and programmability. All endpoints support

I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Conﬁguration Register. A detailed description of the DMA operation is given in Section 10.

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ISP1181A

Full-speed USB peripheral controller

Table 4: Endpoint access and programmability

Endpoint identiﬁer

0 64 (ﬁxed) no yes no control OUT 0 64 (ﬁxed) no yes no control IN 1 programmable supported supported supported programmable 2 programmable supported supported supported programmable 3 programmable supported supported supported programmable 4 programmable supported supported supported programmable 5 programmable supported supported supported programmable 6 programmable supported supported supported programmable 7 programmable supported supported supported programmable 8 programmable supported supported supported programmable 9 programmable supported supported supported programmable 10 programmable supported supported supported programmable 11 programmable supported supported supported programmable 12 programmable supported supported supported programmable 13 programmable supported supported supported programmable 14 programmable supported supported supported programmable

FIFO size (bytes)

[1]

Double buffering

I/O mode access

DMA mode access

Endpoint type

[2]

[1] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1181A transmits); OUT: output from the USB host (ISP1181A receives). The data ﬂow direction is

determined by bit EPDIR in the Endpoint Conﬁguration Register.

9.2 Endpoint FIFO size

The size of the FIFO determines the maximum packet size that the hardware can support for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO storage, disabled endpoints have zero bytes. Table 5 lists the programmable FIFO sizes.

The following bits in the Endpoint Conﬁguration Register (ECR) affect FIFO allocation:

• Endpoint enable bit (FIFOEN)

• Size bits of an enabled endpoint (FFOSZ[3:0])

• Isochronous bit of an enabled endpoint (FFOISO).

Remark: Register changes that affect the allocation of the shared FIFO storage

among endpoints must not be made while valid data is present in any FIFO of the enabled endpoints. Such changes will render all FIFO contents undeﬁned.

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Table 5: Programmable FIFO size

FFOSZ[3:0] Non-isochronous Isochronous

0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes

ISP1181A

Full-speed USB peripheral controller

Each programmable FIFO can be conﬁgured independently via its ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes.

Table 6 showsan exampleof a conﬁguration ﬁtting in the maximumavailable space of

2462 bytes. The total number of logical bytes in the example is 1311. The physical storage capacity used for double buffering is managed by the peripheral hardware and is transparent to the user.

Table 6: Memory conﬁguration example

Physical size (bytes)

64 64 control IN (64 byte ﬁxed) 64 64 control OUT (64 byte ﬁxed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt OUT 16 16 16-byte interrupt IN 128 64 double-buffered 64-byte bulk OUT 128 64 double-buffered 64-byte bulk IN

Logical size (bytes)

Endpoint description

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9.3 Endpoint initialization

In response to the standard USB request, Set Interface, the ﬁrmware must program all 16 ECRs of the ISP1181A in sequence (see Table 4), whether the endpoints are enabled or not. The hardware will then automatically allocate FIFO storage space.

If all endpoints havebeen conﬁgured successfully, the ﬁrmware must return an empty packet to the control IN endpoint to acknowledge success to the host. If there are errors in the endpoint conﬁguration, the ﬁrmware must stall the control IN endpoint.

When reset by hardware or via the USB bus, the ISP1181A disables all endpoints and clears all ECRs, except for the control endpoint which is ﬁxed and always enabled.

Endpoint initialization can be done at any time; however, it is valid only after enumeration.

9.4 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (EPn) of the Interrupt Register (IR) will be set by the SIE. The ﬁrmware then responds to the interrupt and selects the endpoint for processing.

ISP1181A

Full-speed USB peripheral controller

The endpoint interrupt bit will be cleared by reading the Endpoint Status Register (ESR). The ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and packet data can be read from ISP1181A using the Read Buffer command. When the whole packet has been read, the ﬁrmware sends a Clear Buffer command to enable the reception of new packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written to ISP1181A using the Write Buffer command. When the whole packet has been written to the buffer, the ﬁrmware sends a Validate Buffer command to enable data transmission to the host.

9.5 Special actions on control endpoints

Control endpoints require special ﬁrmware actions. The arrival of a SETUP packet ﬂushes the IN bufferand disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microcontroller needs to re-enable these commands by sending an Acknowledge Setup command to both control endpoints.

This ensures that the last SETUP packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the SETUP packet.

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10. DMA transfer

Direct Memory Access (DMA) is a method to transfer data from one location to another in a computer system, without intervention of the central processor (CPU). Many different implementations of DMA exist. The ISP1181A supports two methods:

• 8237 compatible mode: based on the DMA subsystem of the IBM personal

• DACK-only mode: based on the DMA implementation in some embedded RISC

The ISP1181A supports DMA transfer for all 14 conﬁgurable endpoints (see Table 4). Only one endpoint at a time can be selected for DMA transfer.The DMA operation of the ISP1181A can be interleaved with normal I/O mode access to other endpoints.

The following features are supported:

• Single-cycle or burst transfers (up to 16 bytes per cycle)

• Programmable transfer direction (read or write)

• Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,

• Programmable signal levels on pins DREQ, DACK and EOT.

ISP1181A

Full-speed USB peripheral controller

computers (PC, AT and all its successors and clones); this architecture uses the Intel 8237 DMA controller and has separate address spaces for memory and I/O

processors, which has a single address space for both memory and I/O.

short/empty packet

10.1 Selecting an endpoint for DMA transfer

The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA Conﬁguration Register, as shown in Table 7. The transfer direction (read or write) is automatically set by bit EPDIR in the associated ECR, to match the selected endpoint type (OUT endpoint: read; IN endpoint: write).

Asserting input DACK automatically selects the endpoint speciﬁed in the DMA Conﬁguration Register, regardless of the current endpoint used for I/O mode access.

Table 7: Endpoint selection for DMA transfer

Endpoint identiﬁer

1 0010 OUT: read IN: write 2 0011 OUT: read IN: write 3 0100 OUT: read IN: write 4 0101 OUT: read IN: write 5 0110 OUT: read IN: write 6 0111 OUT: read IN: write 7 1000 OUT: read IN: write 8 1001 OUT: read IN: write

9 1010 OUT: read IN: write 10 1011 OUT: read IN: write 11 1100 OUT: read IN: write

EPIDX[3:0] Transfer direction

EPDIR = 0 EPDIR = 1

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ISP1181A

Full-speed USB peripheral controller

Table 7: Endpoint selection for DMA transfer

Endpoint

EPIDX[3:0] Transfer direction

identiﬁer

12 1101 OUT: read IN: write 13 1110 OUT: read IN: write 14 1111 OUT: read IN: write

10.2 8237 compatible mode

The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware Conﬁguration Register (see Table 20). The pin functions for this mode are shown in

Table 8.

Table 8: 8237 compatible mode: pin functions

Symbol Description I/O Function

DREQ DMA request O ISP1181A requests a DMA transfer DACK DMA acknowledge I DMA controller conﬁrms the transfer EOT end of transfer I DMA controller terminates the transfer RD read strobe I instructs ISP1181A to put data on the bus WR write strobe I instructs ISP1181A to get data from the

…continued

EPDIR = 0 EPDIR = 1

bus

The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA controller. It operates as a ‘ﬂy-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1181A in 8237 compatible DMA mode is given in Figure 4.

The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA (Hold Acknowledge). The bus operation is controlled via MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).

DATA1 to DATA15

AD0,

ISP1181A

DREQ

DACK

RAM

Fig 4. ISP1181A in 8237 compatible DMA mode.

MEMR MEMW

DMA

CONTROLLER

8237

DREQ HRQ DACK

IOR IOW

HLDA

CPU

HRQ HLDA

004aaa022

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The following example shows the steps which occur in a typical DMA transfer:

1. ISP1181A receives a data packet in one of its endpoint FIFOs; the packet must

2. ISP1181A asserts the DREQ signal requesting the 8237 for a DMA transfer.

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places the bus control

5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR

6. The 8237 asserts DACK to inform the ISP1181A that it will start a DMA transfer.

7. The ISP1181A now places the byte or word to be transferred on the data bus

8. The8237waits one DMA clock period and then de-asserts MEMW and IOR. This

9. The ISP1181A de-asserts the DREQ signal to indicate to the 8237 that DMA is

10. The 8237 de-asserts the DACK output indicating that the ISP1181A must stop

11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the

12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating

ISP1181A

Full-speed USB peripheral controller

be transferred to memory address 1234H.

signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and asserts HLDA to inform the 8237 that it has control of the bus.

control signals.

lines, because its RD signal was asserted by the 8237.

latches and stores the byte or word at the desired memory location. It also informs the ISP1181A that the data on the bus lines has been transferred.

no longer needed. In Single cycle mode this is done after each byte or word, in Burst mode following the last transferred byte or word of the DMA cycle.

placing data on the bus.

address lines in three-state and de-asserts the HRQ signal, informing the CPU that it has released the bus.

the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the CPU resumes the execution of instructions.

Fora typical bulk transfer the above process is repeated 64 times, once for each byte. After each byte the address register in the DMA controller is incremented and the byte counter is decremented. When using 16-bit DMA, the number of transfers is 32, and address incrementing and byte counter decrementing is done by 2 for each word.

10.3 DACK-only mode

The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware Conﬁguration Register (see Table 20). The pin functions for this mode are shown in

Table 9.Atypical exampleof ISP1181A in DACK-onlyDMA mode is given in Figure 5.

Table 9: DACK-only mode: pin functions

Symbol Description I/O Function

DREQ DMA request O ISP1181A requests a DMA transfer DACK DMA acknowledge I DMA controller conﬁrms the transfer;

also functions as data strobe EOT End-Of-Transfer I DMA controller terminates the transfer RD read strobe I not used WR write strobe I not used

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In DACK-only mode the ISP1181A uses the DACK signal as data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes.

ISP1181A

Full-speed USB peripheral controller

ISP1181A DMA

DREQ DACK

AD0,

DATA1 to DATA15

Fig 5. ISP1181A in DACK-only DMA mode.

10.4 End-Of-Transfer conditions

10.4.1 Bulk endpoints

A DMA transfer to/from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the DMA Conﬁguration Register, see Table 24):

• An external End-Of-Transfer signal occurs on input EOT

• The DMA transfer completes as programmed in the DMA Counter register

(CNTREN = 1)

• A short packet is received on an enabled OUT endpoint (SHORTP = 1)

• DMA operation is disabled by clearing bit DMAEN.

RAM

CONTROLLER

DREQ DACK

RD WR

HRQ

HLDA

CPU

HRQ HLDA

004aaa023

External EOT: When reading from an OUT endpoint, an external EOT will stop the

DMA operation and clear any remaining data in the current FIFO. For a doublebuffered endpoint the other (inactive) buffer is not affected.

When writing to an IN endpoint, an EOT will stop the DMA operation and the data packet in the FIFO (evenif it is smaller than the maximum packet size) will be sent to the USB host at the next IN token.

DMA Counter Register: An EOT from the DMA Counter Register is enabled by

setting bit CNTREN in the DMA Conﬁguration Register. The ISP1181A has a 16-bit DMA Counter Register, which speciﬁes the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the DMA Counter Register. When the internal counter completes the transfer as programmed in the DMA counter, an EOT condition is generated and the DMA operation stops.

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Short packet: Normally, the transfer byte count must be set via a control endpoint

before any DMA transfer takes place. When a short packet has been enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet in the data. This mechanism permits the use of a fully autonomous data transfer protocol.

When reading from an OUT endpoint, reception of a short packet at an OUT token will stop the DMA operation after transferring the data bytes of this packet.

Table 10: Summary of EOT conditions for a bulk endpoint

EOT condition OUT endpoint IN endpoint

EOT input EOT is active EOT is active DMA Counter Register transfer completes as

Short packet short packet is received and

DMAEN bit in DMA Conﬁguration Register

Full-speed USB peripheral controller

programmed in the DMA Counter register

transferred DMAEN = 0

[1]

ISP1181A

transfer completes as programmed in the DMA Counter register

counter reaches zero in the middle of the buffer

DMAEN = 0

[1]

[1] The DMA transfer stops. However, no interrupt is generated.

10.4.2 Isochronous endpoints

A DMA transfer to/from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the DMA Conﬁguration Register, see

Table 24):

• An external End-Of-Transfer signal occurs on input EOT

• The DMA transfer completes as programmed in the DMA Counter register

(CNTREN = 1)

• An End-Of-Packet (EOP) signal is detected

• DMA operation is disabled by clearing bit DMAEN.

Table 11: Recommended EOT usage for isochronous endpoints

EOT condition OUT endpoint IN endpoint

EOT input active do not use preferred DMA Counter Register zero do not use preferred End-Of-Packet preferred do not use

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11. Suspend and resume

11.1 Suspend conditions

The ISP1181A detects a USB suspend status when a constant idle state is present on the USB bus for more than 3 ms.

The bus-powered devices that are suspended must not consume more than 500 µA of current. This is achieved by shutting down power to system components or supplying them with a reduced voltage.

The steps leading up to suspend status are as follows:

1. On detecting a wakeup-to-suspend transition, the ISP1181A sets bit SUSPND in the Interrupt register. This will generate an interrupt if bit IESUSP in the Interrupt Enable register is set.

2. When the ﬁrmware detects a suspend condition, it must prepare all system components for the suspend state:

a. Allsignals connected to the ISP1181A must enter appropriate states to meet

the power consumption requirements of the suspend state.

b. All input pins of the ISP1181A must have a CMOS LOW or HIGH level.

3. In the interrupt service routine, the ﬁrmware must check the current status of the USB bus. When bit BUSTATUS in the Interrupt register is logic 0, the USB bus has left the suspend mode and the process must be aborted. Otherwise, the next step can be executed.

4. To meet the suspend current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit CLKRUN in the Hardware Conﬁguration register.

5. When the ﬁrmware has set and cleared bit GOSUSP in the Mode register, the ISP1181A enters the suspend state. In powered-off application, the ISP1181A asserts output SUSPEND and switches off the internal clocks after 2 ms.

ISP1181A

Full-speed USB peripheral controller

Figure 6 shows a typical timing diagram.

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ISP1181A

Full-speed USB peripheral controller

USB BUS

INT_N

GOSUSP

WAKEUP

SUSPEND

Fig 6. Suspend and resume timing.

In Figure 6:

> 3 ms

suspend interrupt

> 5 ms

idle state

1.8 ms to 2.2 ms

10 ms

K-state

resume

interrupt

004aaa359

0.5 ms to 3.5 ms

• A: indicates the point at which the USB bus enters the idle state.

• B: indicates resume condition, which can be a 20 ms K-state on the USB bus, a

HIGH level on pin WAKEUP, or a LOW level on pin CS.

• C: indicates remote wake-up. The ISP1181A will drive a K-state on the USB bus

for 10 ms after pin WAKEUP goes HIGH or pin CS goes LOW.

• D: after detecting the suspend interrupt, set and clear bit GOSUSP in the Mode

11.1.1 Powered-off application

Figure 7 shows a typical bus-powered modem application using the ISP1181A. The

SUSPEND output switches off powerto the microcontroller and other external circuits during the suspend state. The ISP1181A is woken up through the USB bus (global resume) or by the ring detection circuit on the telephone line.

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