Philips ISP1161A User Manual

ISP1161A

Full-speed Universal Serial Bus single-chip host and device controller

Rev. 03 — 23 December 2004 Product data

1. General description

The ISP1161A is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC). The Host Controller portion of the ISP1161A complies with

Universal Serial Bus Speciﬁcation Rev. 2.0

(12 Mbit/s) and low-speed (1.5 Mbit/s). The Device Controller portion of the ISP1161A also complies with data rates at full-speed (12 Mbit/s). These two USB controllers, the HC and the DC, share the same microprocessor bus interface. They have the same data bus, but different I/O locations. They also have separate interrupt request output pins, separate DMA channels that include separate DMA request output pins and DMA acknowledge input pins. This makes it possible for a microprocessor to control both the USB HC and the USB DC at the same time.

ISP1161A provides two downstream ports forthe USB HC and one upstream port for the USB DC. Each downstream port has an overcurrent (OC) detection input pin and power supply switching control output pin. The upstream port has a V input pin. ISP1161A also provides separate wake-up input pins and suspended status output pins for the USB HC and the USB DC, respectively. This makes power management ﬂexible. The downstream ports for the HC can be connected with any USB compliant devices and hubs that have USB upstream ports. The upstream port for the DC can be connected to any USB compliant USB host and USB hubs that have USB downstream ports.

, supporting data rates at full-speed

Universal Serial Bus Speciﬁcation Rev. 2.0

BUS

, supporting

detection

The HC is adapted from the

Release 1.0a

The DC is compliant with most USB device class speciﬁcations such as Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices and Human Interface Devices.

ISP1161A is well suited for embedded systems and portable devices that require a USB host only, a USB device only, or a combination of a conﬁgurable USB host and USB device. ISP1161A brings high ﬂexibility to the systems that have it built-in. For example, a system that uses an ISP1161A allows it not only to be connected to a PC or USB hub with a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse. Therefore, the ISP1161A enables peer-to-peer connectivity between embedded systems. An interesting application example is to connect an ISP1161A HC with an ISP1161A DC.

Consider an example of an ISP1161A being used in a Digital Still Camera (DSC) design. Figure 1 shows an ISP1161A being used as a USB DC. Figure 2 shows an ISP1161A being used as a USB HC. Figure 3 shows an ISP1161A being used as a USB HC and a USB DC at the same time.

, referred to as OHCI in the rest of this document.

Open Host Controller Interface Speciﬁcation for USB

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

EMBEDDED SYSTEM

(host)

USB I/F

Fig 1. ISP1161A operating as a USB device.

EMBEDDED SYSTEM

µP

ISP1161A

HOST/

DEVICE

DSC

USB cable

µP SYSTEM

MEMORY

µP bus I/F

USB host

USB I/F

µP

ISP1161A

USB device

USB cable

µP SYSTEM

MEMORY

µP bus I/F

HOST/

DEVICE

DSC

004aaa080

PRINTER

(device)

USB I/F

004aaa081

Fig 2. ISP1161A operating as a stand-alone USB host.

EMBEDDED SYSTEM

ISP1161A

HOST/

DEVICE

µP SYSTEM

MEMORY

µP bus I/F

USB host

PRINTER

(device)

USB I/FUSB I/F

USB I/F

004aaa082

(host)

µP

DSC

USB cable USB cable

USB I/F

USB device

Fig 3. ISP1161A operating as both USB host and device simultaneously.

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2. Features

ISP1161A

Full-speed USB single-chip host and device controller

■ Complies with

■ The Host Controller portion of the ISP1161A supports data transfer at full-speed

(12 Mbit/s) and low-speed (1.5 Mbit/s); the Device Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s)

■ Combines the HC and the DC in a single chip

■ On-chip DC complies with most USB device class speciﬁcations

■ Both the HC and the DC can be accessed by an external microprocessor via

separate I/O port addresses

■ Selectable one or two downstream ports for the HC and one upstream port for the

■ High-speed parallel interface to most of the generic microprocessors and

Reduced Instruction Set Computer (RISC) processors such as:

◆ Hitachi® SuperH™ SH-3 and SH-4

◆ MIPS-based™ RISC

◆ ARM7™, ARM9™, StrongARM

■ Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC,

11.1 Mbyte/s data transfer rate between the microprocessor and the DC

■ Supports single-cycle and burst mode DMA operations

■ Up to 14 programmable USB endpoints with 2 ﬁxed control IN/OUT endpoints for

the DC

■ Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes)

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer for both DC transfers and HC isochronous (ISO) transactions

■ 6 MHz crystal oscillator with integrated PLL for low EMI

■ Controllable LazyClock (100 kHz ± 50 %) output during ‘suspend’

■ Clock output with programmable frequency (3 MHz to 48 MHz)

■ Software controlled connection to the USB bus (SoftConnect™) on upstream port

for the DC

■ Good USB connection indicator that blinks with trafﬁc (GoodLink™) for the DC

■ Software selectable internal 15 kΩ pull-down resistors for HC downstream ports

■ Dedicated pins for suspend sensing output and wake-up control input for ﬂexible

applications

■ Global hardware reset input pin and separate internal software reset circuits for

HC and DC

■ Operation from a 5 V or a 3.3 V power supply

■ Operating temperature range −40 °Cto+85 °C

■ Available in two LQFP64 packages (SOT314-2 and SOT414-1).

Universal Serial Bus Speciﬁcation Rev. 2.0

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Philips Semiconductors

Full-speed USB single-chip host and device controller

ISP1161A

3. Applications

■ Personal Digital Assistant (PDA)

■ Digital camera

■ Third-generation (3-G) phone

■ Set-Top Box (STB)

■ Information Appliance (IA)

■ Photo printer

■ MP3 jukebox

■ Game console.

4. Ordering information

Table 1: Ordering information

Type number Package

Name Description Version

ISP1161ABD LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 ISP1161ABM LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 7 × 7 × 1.4 mm SOT414-1

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xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

6 MHz

5. Block diagram

Philips Semiconductors

to/from

microprocessor

H_WAKEUP

H_SUSPEND

NDP_SEL

D0 to D15

RD CS

A1 A0

DACK2 DACK1

EOT DREQ2 DREQ1

INT2 INT1

D_WAKEUP

D_SUSPEND

RESET

40 42 33 2 to 7,

9 to 14, 16, 17, 63, 64

RESET

AGND

ISP1161A

HOST BUS

INTERFACE

DEVICE BUS

INTERFACE

3.3 V

reg(3.3)

hold2

internal

reset

internal

supply

245857

hold1

22 21 23 60 59 28 27 34 26 25 30 29

37 36

DGND

HOST/

DEVICE

AUTOMUX

1, 8, 15, 18, 35, 45, 62

POWER-ON

VOLTAGE

REGULATOR

HOST CONTROLLER

ALT RAM

ITL0

(PING RAM)

PHILIPS SLAVE

HOST CONTROLLER

Host bus

Device bus

DEVICE

CONTROLLER

PING

PONG

RAM

DEVICE CONTROLLER

RAM

ITL1

(PONG RAM)

GoodLink

RECOVERY

CLOCK

PLL

CLOCK

PROGRAMMABLE

DIVIDER

413819

CLKOUT

XTAL1XTAL2 43

OVERCURRENT

TRANSCEIVER

SoftConnect

POWER

SWITCHING

DETECTION

USB

4×

15 kΩ

USB

n.c.

GND

1.5 kΩ

61, 20

3.3 V

46 47 54 55

50 51 52 53

39 48 49

004aaa083

H_PSW1 H_PSW2 H_OC1 H_OC2

H_DM1 H_DP1

H_DM2 H_DP2

D_VBUS D_DM D_DP

USB bus

downstream

ports

USB bus upstream

port

Full-speed USB single-chip host and device controller

ISP1161A

Fig 4. Block diagram.

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

POWER-ON

RESET

ITL0 RAM

MANAGEMENT

Host

bus I/F

µP interface

BUS I/F

DMA

HANDLER

µP

HANDLER

Fig 5. Host controller sub-block diagram.

POWER-ON

RESET

DMA HANDLER

Device

bus I/F

BUS I/F

µP HANDLER

ATL RAM

ITL1 RAM

MEMORY

UNIT

Host controller sub-blocks

MANAGEMENT UNIT

INTEGRATED

RAM

MEMORY

ACCESS

USB

STATE

FRAME

MANAGE-

MENT

PDT_LIST

PROCESS

PHILIPS SIE

SoftConnect

TRANSCEIVER

USB InterfacePhilips sHC coreMemory block

clock

recovery

PHILIPS

SIE

USB

TRANSCEIVER

3.3 V

USB

MGT930

USB bus

H_DP1 H_DM1 H_DP2 H_DM2

USB bus

D_DP D_DM

clock recovery

EP HANDLER

Device controller sub-blocks

GoodLink

MGT931

Fig 6. Device controller sub-block diagram.

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6. Pinning information

6.1 Pinning

ISP1161A

Full-speed USB single-chip host and device controller

DGND

D2 D3 D4 D5 D6 D7

DGND

D9 D10 D11 D12 D13

DGND

D14

DGND

n.c.A1A0

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

reg(3.3)

ISP1161ABD ISP1161ABM

AGND 57

VCCH_OC2 56

H_OC1 54

H_DP2 53

H_DM2 52

H_DP1 51

H_DM1 50

D_DP49

D_DM H_PSW2

H_PSW1

DGND

45 44

XTAL2

XTAL1

H_SUSPEND CLKOUT

41 40

H_WAKEUP

D_VBUS

GL D_WAKEUP

D_SUSPEND

DGND

EOT

NDP_SEL

D15

DGND

hold1

20 n.c.

22 RD

23 WR

hold2

DREQ1

DACK1

DREQ2

DACK2

INT1

INT2

TEST

004aaa085

RESET

Fig 7. Pin conﬁguration LQFP64.

6.2 Pin description

Table 2: Pin description for LQFP64

Symbol

DGND 1 - digital ground D2 2 I/O bit 2 of bidirectional data; slew-rate controlled; TTL input;

D3 3 I/O bit 3 of bidirectional data; slew-rate controlled; TTL input;

D4 4 I/O bit 4 of bidirectional data; slew-rate controlled; TTL input;

D5 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input;

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[1]

Pin Type Description

three-state output

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

Table 2: Pin description for LQFP64

Symbol

[1]

Pin Type Description

…continued

D6 6 I/O bit 6 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D7 7 I/O bit 7 of bidirectional data; slew-rate controlled; TTL input;

three-state output DGND 8 - digital ground D8 9 I/O bit 8 of bidirectional data; slew-rate controlled; TTL input;

three-state output D9 10 I/O bit 9 of bidirectional data; slew-rate controlled; TTL input;

three-state output D10 11 I/O bit 10 of bidirectional data; slew-rate controlled; TTL input;

three-state output D11 12 I/O bit 11 of bidirectional data; slew-rate controlled; TTL input;

three-state output D12 13 I/O bit 12 of bidirectional data; slew-rate controlled; TTL input;

three-state output D13 14 I/O bit 13 of bidirectional data; slew-rate controlled; TTL input;

three-state output DGND 15 - digital ground D14 16 I/O bit 14 of bidirectional data; slew-rate controlled; TTL input;

three-state output D15 17 I/O bit 15 of bidirectional data; slew-rate controlled; TTL input;

three-state output DGND 18 - digital ground V

hold1

19 - voltage holding pin; internallyconnected to the V

pins. When VCC is connected to 5 V, this pin will

hold2

output 3.3 V, hence do not connect it to 5 V. When V

reg(3.3)

and

connected to 3.3 V, this pin can either be connected to

3.3 V or left unconnected. In all cases, decouple this pin to

DGND. n.c. 20 - no connection CS 21 I chip select input RD 22 I read strobe input WR 23 I write strobe input V

hold2

24 - voltage holding pin; internallyconnected to the V

pins. When VCC is connected to 5 V, this pin will

hold1

output 3.3 V, hence do not connect it to 5 V. When V

reg(3.3)

and

connected to 3.3 V, this pin can either be connected to

3.3 V or left unconnected. In all cases, decouple this pin to

DGND. DREQ1 25 O HC DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161A wants to start a

DMA transfer; see Section 10.4.1 DREQ2 26 O DC DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161A wants to start a

DMA transfer; see Section 13.1.4 DACK1 27 I HC DMA acknowledgeinput; when not in use,this pin must

be connected to V

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via an external 10 kΩ resistor

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

Table 2: Pin description for LQFP64

Symbol

[1]

Pin Type Description

…continued

DACK2 28 I DC DMA acknowledgeinput; when not in use,this pin must

be connected to V

via an external 10 kΩ resistor

INT1 29 O HC interrupt output; programmable level, edge triggered

and polarity; see Section 10.4.1 INT2 30 O DC interrupt output; programmable level, edge triggered

and polarity; see Section 13.1.4 TEST 31 O test output; used for test purposes only; this pin is not

connected during normal operation RESET 32 I reset input (Schmitt trigger); a LOW level produces an

asynchronous reset (internal pull-up resistor) NDP_SEL 33 I indicates to the HC software the Number of Downstream

Ports (NDP) present:

0 — select 1 downstream port

1 — select 2 downstream ports

only changes the value of the NDP ﬁeld in the

HcRhDescriptorA register; both ports will always be

enabled; see Section 10.3.1

(internal pull-up resistor) EOT 34 I DMA master device to inform the ISP1161A of end of DMA

transfer; active level is programmable; see Section 10.4.1 DGND 35 - digital ground D_SUSPEND 36 O DC ‘suspend’ state indicator output; active HIGH D_WAKEUP 37 I DC wake-up input; generates a remote wake-up from

‘suspend’ state (active HIGH); when not in use, this pin

must be connected to DGND via an external 10 kΩ resistor

(internal pull-down resistor) GL 38 O GoodLink LED indicator output (open-drain, 8 mA); the

LED is default ON, blinks OFF upon USB trafﬁc; to connect

a LED use a series resistor of 470 Ω (V

330 Ω (V

= 3.3 V)

D_VBUS 39 I DC USB upstream port V

sensing input; when not in

BUS

= 5.0 V) or

use, this pin must be connected to DGND via a 1 MΩ

resistor H_WAKEUP 40 I HC wake-up input; generates a remote wake-up from

‘suspend’ state (active HIGH); when not in use, this pin

must be connected to DGND via an external 10 kΩ resistor

(internal pull-down resistor) CLKOUT 41 O programmable clock output (3 MHz to 48 MHz); default

12 MHz H_SUSPEND 42 O HC ‘suspend’ state indicator output; active HIGH XTAL1 43 I crystal input; connected directly to a 6 MHz crystal; when

XTAL1 is connected to an external clock source, pin XTAL2

must be left open XTAL2 44 O crystal output; connected directly to a 6 MHz crystal; when

pin XTAL1 is connected to an external clock source, this

pin must be left open

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ISP1161A

Full-speed USB single-chip host and device controller

Table 2: Pin description for LQFP64

Symbol

[1]

Pin Type Description

…continued

DGND 45 - digital ground H_PSW1 46 O power switching control output for downstream port 1;

open-drain output H_PSW2 47 O power switching control output for downstream port 2;

open-drain output D_DM 48 AI/O USB D− data line for DC upstream port; when not in use,

this pin must be left open D_DP 49 AI/O USB D+ data line for DC upstream port; when not in use,

this pin must be left open H_DM1 50 AI/O USB D− data line for HC downstream port 1 H_DP1 51 AI/O USB D+ data line for HC downstream port 1 H_DM2 52 AI/O USB D− data line for HC downstream port 2; when not in

use, this pin must be left open H_DP2 53 AI/O USB D+ data line for HC downstream port 2; when not in

use, this pin must be left open H_OC1 54 I overcurrent sensing input for HC downstream port 1 H_OC2 55 I overcurrent sensing input for HC downstream port 2 V

56 - power supply voltage input (3.0 V to 3.6 V or

4.75 V to 5.25 V). This pin connects to the internal 3.3 V

regulator input. When connected to 5 V, the internal

regulator will output 3.3 V to pins V

reg(3.3),Vhold1

and V

hold2

When connected to 3.3 V, it will bypass the internal

regulator. AGND 57 - analog ground V

reg(3.3)

58 - internal 3.3 V regulator output; when the VCC pin is

connected to 5 V, this pin outputs 3.3 V. When the V

is connected to 3.3 V, connect this pin to 3.3 V. A0 59 I address input; selects command (A0 = 1) or data (A0 = 0) A1 60 I address input; selects AutoMux switching to DC (A1 = 1) or

AutoMux switching to HC (A1 = 0); see Table 3 n.c. 61 - no connection DGND 62 - digital ground D0 63 I/O bit 0 of bidirectional data; slew-rate controlled; TTL input;

three-state output D1 64 I/O bit 1 of bidirectional data; slew-rate controlled; TTL input;

three-state output

[1] Symbol names with an overscore (e.g. NAME) represent active LOW signals.

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7. Functional description

7.1 PLL clock multiplier

A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL.

7.2 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4 times over-sampling principle. It is able to track jitter and frequency drift as speciﬁed in the

7.3 Analog transceivers

Three sets of transceivers are embedded in the chip: two are used for downstream ports with USB connector type A; one is used for upstream port with USB connector type B. The integrated transceivers are compliant with the

Speciﬁcation Rev. 2.0

through external termination resistors.

ISP1161A

Full-speed USB single-chip host and device controller

Universal Serial Bus Speciﬁcation Rev. 2.0

. They interface directly with the USB connectors and cables

Universal Serial Bus

7.4 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no ﬁrmware intervention. The functions of this block include: synchronization pattern recognition, parallel to serial conversion, bit (de)stufﬁng, CRC checking and generation, Packet IDentiﬁer (PID) veriﬁcation and generation, address recognition, handshake evaluation and generation. There are separate SIEs in both the HC and the DC.

7.5 SoftConnect

The connection to the USB is accomplished by bringing D+ (for full-speed USB devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1161A DC, the 1.5 kΩ pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external or system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB. Re-initialization of the USB connection can also be performed without disconnecting the cable.

The ISP1161A DC will check for USB V established. V

Remark: The tolerance of the internal resistors is 25 %. This is higher than the 5 % tolerance speciﬁed by the USB speciﬁcation. However, the overall voltage speciﬁcation for the connection can still be met with a good margin. The decision to make use of this feature lies with the USB equipment designer.

sensing is provided through pin D_VBUS.

BUS

availability before the connection can be

BUS

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7.6 GoodLink

Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration, the LED indicator will blink on momentarily. When the DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161A the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off.

This feature provides a user-friendly indication of the status of the USB device, the connected hub and the USB trafﬁc. It is a useful ﬁeld diagnostics tool for isolating faulty equipment. It can therefore help to reduce ﬁeld support and hotline overhead.

8. Microprocessor bus interface

8.1 Programmed I/O (PIO) addressing mode

A generic PIO interface is deﬁned for speed and ease-of-use. It also allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1161A appears as a memory device with a 16-bit data bus and uses only two address lines: A1 and A0 to access the internal control registers and FIFO buffer RAM. Therefore, the ISP1161A occupies only four I/O ports or four memory locations of a microprocessor. External microprocessors can read from or write to the ISP1161A internal control registers and FIFO bufferRAM through the Programmed I/O (PIO) operating mode. Figure 8 shows the Programmed I/O interface between a microprocessor and an ISP1161A.

ISP1161A

Full-speed USB single-chip host and device controller

MICRO-

PROCESSOR

D[15:0

IRQ1 IRQ2

µP bus I/F

]

A2 A1

D[15:0

RD WR CS A1 A0

INT1 INT2

]

ISP1161A

004aaa086

Fig 8. Programmed I/O interface between a microprocessor and an ISP1161A.

8.2 DMA mode

The ISP1161A also provides DMA mode for external microprocessors to access its internal FIFO buffer RAM. Data can be transferred by DMA operation between a microprocessor’s system memory and the ISP1161A internal FIFO buffer RAM.

Remark: The DMA operation must be controlled by the external microprocessor system DMA controller (Master).

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Figure 9 shows the DMA interface between a microprocessor system and the

ISP1161A. The ISP1161A provides two DMA channels:

• DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer

• DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer

The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1161A provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConﬁguration register (21H - read, A1H - write) enables the ISP1161A HC internal DMA counter for DMA transfer. When the DMA counter reaches the value set in the HcTransferCounter register (22H - read, A2H - write), an internal EOT signal will be generated to terminate the DMA transfer.

ISP1161A

Full-speed USB single-chip host and device controller

between a microprocessor’s system memory and ISP1161A HC internal FIFO buffer RAM

between a microprocessor system memory and the ISP1161A DC internal FIFO buffer RAM.

µP bus I/F

]

D[15:0

MICRO-

PROCESSOR

DACK1

DREQ1

DACK2

DREQ2

EOT

Fig 9. DMA interface between a microprocessor and an ISP1161A.

8.3 Control register access by PIO mode

8.3.1 I/O port addressing

Table 3 shows the ISP1161A I/O port addressing. Complete decoding of the I/O port

address should include the chip select signal CS and the address lines A1 and A0. However, the direction of the access of the I/O ports is controlled by the RD and WR signals. When RD is LOW, the microprocessor reads data from the ISP1161A data port. When WR is LOW, the microprocessor writes a command to the command port, or writes data to the data port.

D[15:0

RD WR

DACK1 DREQ1

DACK2 DREQ2

EOT

]

ISP1161A

004aaa087

Table 3: I/O port addressing

Port Pin CS Pin A1 Pin A0 Access Data bus width Description

0 LOW LOW LOW R/W 16 bits HC data port 1 LOW LOW HIGH W 16 bits HC command port 2 LOW HIGH LOW R/W 16 bits DC data port 3 LOW HIGH HIGH W 16 bits DC command port

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Figure 10 and Figure 11 illustrate how an external microprocessor accesses the

ISP1161A internal control registers.

Fig 10. A microprocessor accessing an HC or a DC via an automux switch.

Full-speed USB single-chip host and device controller

AUTOMUX

DC/HC

µP bus I/F

When A1 = 0, the microprocessor accesses the HC. When A1 = 1, the microprocessor accesses the DC.

CMD/DATA

SWITCH

command port

Host or Device

bus I/F

data port

Host bus I/F

Device bus I/F

MGT935

ISP1161A

Commands

Command register

When A0 = 0, the microprocessor accesses the data port. When A0 = 1, the microprocessor accesses the command port.

Fig 11. A microprocessor accessing internal control registers.

8.3.2 Register access phases

The ISP1161A register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1161A to the next register to be accessed. A command is 8 bits long. On a microprocessor’s 16-bit data bus, a command occupies the lower byte, with the upper byte ﬁlled with zeros.

Figure 12 shows a complete 16-bit register access cycle for the ISP1161A. The

microprocessor writes a command code to the command port, and then reads or writes the data word from or to the data port. Take the example of a microprocessor attempting to read the ISP1161A’s ID. The ID is kept in the HC’s HcChipID register (index 27H, read only). The 16-bit register access cycle is therefore:

1. Microprocessor writes the command code of 27H (0027H in 16-bit width) to the HC command port

2. Microprocessor reads the data word of the chip’s ID from the HC data port.

Control registers

MGT936

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ISP1161A

Full-speed USB single-chip host and device controller

16-bit register access cycle

write command

(16 bits)

read/write data

(16 bits)

MGT937

Fig 12. 16-bit register access cycle.

Most of the ISP1161A internal control registers are 16 bits wide. Some of the internal control registers have 32-bit width. Figure 13 shows how the 32-bit internal control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor ﬁrst reads or writes the lower 16-bits, followed by the upper 16-bits.

32-bit register access cycle

write command

(16 bits)

read/write data

(lower 16 bits)

read/write data

(upper 16 bits)

MGT938

Fig 13. 32-bit register access cycle.

To further describe the complete access cycles of the internal control registers, the status of some pins of the microprocessor bus interface are shown in Figure 14 and

Figure 15 for the HC and the DC respectively.

A1, A0

D[15:0

]

01 00 00

HC command

code

Fig 14. Accessing HC control registers.

HC register data

(lower word)

readread

writewritewrite

writewrite

readread

HC register data

(upper word)

MGT939

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ISP1161A

Full-speed USB single-chip host and device controller

A1, A0

D[15:0

]

11 10 10

DC command

code

DC register data

(lower word)

readread

writewritewrite

writewrite

readread

DC register data

(upper word)

Fig 15. Accessing DC control registers.

8.4 FIFO buffer RAM access by PIO mode

Since the ISP1161A internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register ﬁelds. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases.

FIFO buffer RAM access cycle (transfer counter = 2N)

MGT940

write command

(16 bits)

read/write data

#1 (16 bits)

Fig 16. Internal FIFO buffer RAM access cycle.

Figure 16 shows a complete access cycle of the HC internal FIFO buffer RAM. For a

write cycle, the microprocessor ﬁrst writes the FIFO buffer RAM’s command code to the command port, and then writes the data words one by one to the data port until half of the transfer’s byte count is reached. The HcTransferCounter register (22H read, A2H - write) is used to specify the byte count of a FIFO buffer RAM’s read cycle or write cycle. Every access cycle must be in the same access direction. The read cycle procedure is similar to the write cycle.

For access to the DC FIFO buffer RAM access, see Section 13.

read/write data

#2 (16 bits)

read/write data

#N (16 bits)

MGT941

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8.5 FIFO buffer RAM access by DMA mode

The DMA interface between a microprocessor and the ISP1161A is shown in

Figure 9.

When doing a DMA transfer, at the beginning of every burst the ISP1161A outputs a DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for DC). After receiving this signal, the microprocessor will reply with a DMA acknowledge via the DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA transfer through the data bus. In the DMA mode, the microprocessor must issue a read or write signal to the ISP1161A RD or WR pin. The ISP1161A will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer.

ISP1161A supports both external and internal EOT signals. The external EOT signal is received as input on pin EOT, and generally comes from the external microprocessor. The internal EOT signal is generated by the ISP1161A internally.

To select either EOT method, set the appropriate DMA conﬁguration register (see

Section 10.4.2 and Section 13.1.6). For example, for the HC, setting

DMACounterSelect bit of the HcDMAConﬁguration register (21H - read, A1H - write) to logic 1 will enable the DMA counter for DMA transfer. When the DMA counter reaches the value of the HcTransferCounter register, the internal EOT signal will be generated to terminate the DMA transfer.

ISP1161A

Full-speed USB single-chip host and device controller

ISP1161A supports either single-cycle DMA operation or burst mode DMA operation.

DREQ

DACK

RD or WR

]

D[15:0

data #1 data #2 data #N

EOT

004aaa103

N = 1/2 byte count of transfer data.

Fig 17. DMA transfer in single-cycle mode.

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DREQ

DACK

RD or WR

]

D[15:0

data #1 data #K data #2K data #Ndata #(K+1) data #(N−K+1)

EOT

N = 1/2 byte count of transfer data, K = number of cycles/burst.

Fig 18. DMA transfer in burst mode.

In Figure 17 and Figure 18, the hardware is conﬁgured such that DREQ is active HIGH and DACK is active LOW.

ISP1161A

Full-speed USB single-chip host and device controller

004aaa104

8.6 Interrupts

The ISP1161A has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2).

8.6.1 Pin conﬁguration

The interrupt output signals have four conﬁguration modes: Mode 0 Level trigger, active LOW (default at power-up)

Mode 1 Level trigger, active HIGH Mode 2 Edge trigger, active LOW Mode 3 Edge trigger, active HIGH.

Figure 19 shows these four interrupt conﬁguration modes. They are programmable

via the HcHardwareConﬁguration register (see Section 10.4.1), which are also used to disable or enable the signals.

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Full-speed USB single-chip host and device controller

INT

Mode 0 level triggered, active LOW

INT

Mode 1 level triggered, active HIGH

INT

Mode 2 edge triggered, active LOW

INT

Mode 3 edge triggered, active HIGH

Fig 19. Interrupt pin operating modes.

8.6.2 HC’s interrupt output pin (INT1)

To program the four conﬁguration modes of the HC’s interrupt output signal (INT1), set bits InterruptPinTrigger and InterruptOutputPolarity of the HcHardwareConﬁguration register (20H - read, A0H - write). Bit InterruptPinEnableis used as the master enable setting for pin INT1.

INT active

166 ns

INT active

166 ns

clear or disable INT

MGT944

INT1 has many associated interrupt events, as shown as in Figure 20. The interrupt events of the HcµPInterrupt register (24H - read, A4H - write) changes

the status of pin INT1 when the corresponding bits of the HcµPInterruptEnable register (25H - read, A5H - write) and pin INT1’s global enable bit (InterruptPinEnable of the HcHardwareConﬁguration register) are all set to enable status.

However, events that come from the HcInterruptStatus register (03H - read, 83H write) affect only the OPR_Reg bit of the HcµPInterrupt register. They cannot directly change the status of pin INT1.

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ISP1161A

Full-speed USB single-chip host and device controller

HcInterruptEnable

MIE

RHSC

FNO

UE RD SF SO

RHSC

FNO

UE RD SF SO

HcInterruptStatus

group 2

HcµPInterrupt

ATLInt

SOFITLInt

AllEOTInterrupt

INT1

OPR_Reg

HCSuspended

group 1

ClkReady

LATCH

HcµPInterruptEnable

SOFITLInt

ATLInt

AllEOTInterrupt

HcHardwareConfiguration

InterruptPinEnable

OPR_Reg

HCSuspended

ClkReady

MGT945

Fig 20. HC interrupt logic.

There are two groups of interrupts represented by group 1 and group 2 in Figure 20. A pair of registers control each group.

Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus register). On occurrence of any of these events, the corresponding bit would be set to logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1, the 6-input OR gate would output logic 1. This output is ANDed with the value of MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause bit OPR in the HcµPInterrupt register to be set to logic 1.

Group 1 contains six possible interrupt events, one of which is the output of group 2 interrupt sources. The HcµPInterrupt and HcµPInterruptEnable registers work in the same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt group 2. The output from the 6-input OR gate is connected to a latch, which is controlled by InterruptPinEnable (bit 0 of the HcHardwareConﬁguration register).

In the eventin which the software wishes to temporarily disable the interrupt output of the ISP1161A Host Controller, the following procedure should be followed:

1. Make sure that bit InterruptPinEnable in the HcHardwareConﬁguration register is set to logic 1.

2. Clear all bits in the HcµPInterrupt register.

3. Set bit InterruptPinEnable to logic 0.

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To re-enable the interrupt generation:

1. Set all bits in the HcµPInterrupt register.

2. Set bit InterruptPinEnable to logic 1.

Remark: Bit InterruptPinEnable in the HcHardwareConﬁguration register latches the interrupt output. When this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operations on the interrupt control registers.

If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal without clearing the HcµPInterrupt register, the following procedure should be followed:

1. Make sure that bit InterruptPinEnable is set to logic 1.

2. Clear all bits in the HcµPInterruptEnable register.

3. Set bit InterruptPinEnable to logic 0.

To re-enable the interrupt generation:

1. Set all bits in the HcµPInterruptEnable register according to the HCD

2. Set bit InterruptPinEnable to logic 1.

ISP1161A

Full-speed USB single-chip host and device controller

requirements.

8.6.3 DC interrupt output pin (INT2)

The four conﬁguration modes of DC’s interrupt output pin INT2 can also be programmed by setting bits INTPOL and INTLVL of the DcHardwareConﬁguration register (BBH - read, BAH - write). Bit INTENA of the DcMode register (B9H - read, B8H - write)is used to enable pin INT2. Figure 21 shows the relationship between the interrupt events and pin INT2.

Each of the indicated USB events is logged in a status bit of the DcInterrupt register. Corresponding bits in the Interrupt Enable register determine whether or not an event will generate an interrupt.

Interrupts can be masked globally by means of the INTENA bit of the DcMode register (see Table 81).

The active level and signalling mode of the INT output is controlled by the INTPOL and INTLVL bits of the DcHardwareConﬁguration register (see Table 83). Default settings after reset are active LOW and level mode. When pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1.

Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the DcInterrupt register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated DcEndpointStatus register.

Bit BUSTATUS follows the USB bus status exactly, allowing the ﬁrmware to get the current bus status when reading the DcInterrupt register.

SETUP and OUT token interrupts are generated after the DC has acknowledged the associated data packet. In bulk transfer mode, the DC will issue interrupts for every ACK received for an OUT token or transmitted for an IN token.

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In isochronous mode, an interrupt is issued upon each packet transaction. The ﬁrmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt Enable register. If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows the ﬁrmware to keep data transfer synchronized with the host. After 3 missed SOF events, the DC will enter ‘suspend’ state.

An alternative way of handling isochronous data transfer is to enable both the SOF and the PSOF interrupts and disable the interrupt for each isochronous endpoint.

DcInterrupt register

RESET

SUSPND

RESUME

EP14

EP0IN

EP0OUT

IERST

IESUSP

IERESM

IESOF

IEP14

IEP0IN

IEP0OUT

IEEOT

DcInterruptEnable register

SOF

...

EOT

...

MGT946

ISP1161A

Full-speed USB single-chip host and device controller

. .

DcMode register

INTENA

LATCH

INT2

Fig 21. DC interrupt logic.

Interrupt control: Bit INTENA in the DcMode register is a global enable/disable bit.

The behavior of this bit is given in Figure 22.

INT2 pin

INTENA = 0

(during this time,

an interrupt event

occurs. For example,

SOF asserted.)

Pin INT2: HIGH = de-assert; LOW= assert (individual interrupts are enabled).

Fig 22. Behavior of bit INTENA.

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INTENA = 1

SOF asserted

INTENA = 0

SOF asserted

004aaa198

Philips Semiconductors

Event A (see Figure 22): When an interrupt eventoccurs (for example, SOF interrupt) with bit INTENA set to logic 0, an interrupt will not be generated at pin INT2. However, it will be registered in the corresponding DcInterrupt register bit.

Event B (see Figure 22): When bit INTENA is set to logic 1, pin INT2 is asserted because bit SOF in the DcInterrupt register is already asserted.

Event C (see Figure 22): If the ﬁrmware sets bit INTENA to logic 0, pin INT2 will still be asserted. The bold dashed line shows the desired behavior of pin INT2.

De-assertion of pin INT2 can be achieved in the following manner. Bits[23:8] of the DcInterrupt register are endpoint interrupts. These interrupts are cleared on reading their respective DcEndpointStatus register. Bits[7:0] of the DcInterrupt register are bus status and EOT interrupts that are cleared on reading the DcInterrupt register. Make sure that bit INTENA is set to logic 1 when you perform the clear interrupt commands.

For more information on interrupt control, see Section 13.1.3, Section 13.1.5 and

Section 13.3.6.

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Full-speed USB single-chip host and device controller

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9. USB host controller (HC)

9.1 HC’s four USB states

The ISP1161A USB HC has four USB states − USBOperational, USBReset, USBSuspend, and USBResume − that deﬁne the HC’s USB signaling and bus states responsibilities.

ISP1161A

Full-speed USB single-chip host and device controller

USBOperational write

USBSuspend write

Fig 23. ISP1161A HC USB states.

The USB states are reﬂected in the HostControllerFunctionalState ﬁeld of the HcControl register (01H - read, 81H - write), which is located at bits 7 and 6 of the register.

USBOperational

USBSuspend

USBOperational write

USBResume

USBResume write

remote wake-up

USBReset write

USBReset

hardware or software

reset

USBReset write

MGT947

The Host Controller Driver (HCD) can perform only the USB state transitions shown in Figure 23.

Remark: The Software Reset in Figure 23 is not caused by the HcSoftwareReset command. It is caused by the HostControllerReset ﬁeld of the HcCommandStatus register (02H - read, 82H - write).

9.2 Generating USB trafﬁc

USB trafﬁc can be generated only when the ISP1161A USB HC is in the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState ﬁeld of the HcControl register before generating USB trafﬁc.

A simplistic ﬂow diagram showing when and how to generate USB trafﬁc is shown in

Figure 24. For more detail, refer to the

protocol and ISP1161A USB HC register usage.

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USB Speciﬁcation Revision 2.0

about the

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

Reset

HC state =

Initialize

Entry

USBOperational

USB traffic?

HC informs HCD of

USB traffic results

Fig 24. ISP1161A HC USB transaction loop

The USB trafﬁc blocks are:

• Reset

This includes hardware reset by pin RESET and software reset by the HcSoftwareReset command (A9H). The reset function will clear all the HC’s internal control registers to their reset status. After reset, the HCD must initialize the ISP1161A USB HC by setting some registers.

• Initialize HC

It includes:

– Setting the physical size for the HC’s internal FIFO buffer RAM by setting the

HcITLBufferLength register (2AH - read, AAH - write) and the HcATLBufferLength register (2BH - read, ABH - write)

– Setting the HcHardwareConﬁguration register according to requirements – Clearing interrupt events, if required – Enabling interrupt events, if required – Setting the HcFmInterval register (0DH - read, 8DH - write) – Setting the HC’s Root Hub registers – Setting the HcControl register to move the HC into USBOperational state

9.3 PTD data structure

The Philips Transfer Descriptor (PTD) data structure provides communication between the HCD and the ISP1161A USB HC. The PTD data contains information required by the USB trafﬁc. PTD data consists of a PTD followed by its payload data, as shown in Figure 25.

top

bottom

Fig 25. PTD data in FIFO buffer RAM.

FIFO buffer RAM

PTD

payload data

PTD

payload data

PTD

payload data

PTD data #1

PTD data #2

PTD data #N

MGT949

The PTD data structure is used by the HC to deﬁne a buffer of data that will be moved to or from an endpoint in the USB device. This data buffer is set up for the current frame (1 ms frame) by the HCD. The payload data forevery transferin the frame must have a PTD as a header to describe the characteristics of the transfer. PTD data is DWORD aligned.

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ISP1161A

Full-speed USB single-chip host and device controller

9.3.1 PTD data header deﬁnition

The PTD forms the header of the PTD data. It tells the HC the transfer type, where the payload data goes, and the payload data’s actual size. A PTD is an 8 byte data structure that is very important for HCD programming.

Table 4: Philips Transfer Descriptor (PTD): bit allocation

Bit 7 6 5 4 3 2 1 0 Byte 0 ActualBytes[7:0] Byte 1 CompletionCode[3:0] Active Toggle ActualBytes[9:8] Byte 2 MaxPacketSize[7:0] Byte 3 EndpointNumber[3:0] Last Speed MaxPacketSize[9:8] Byte 4 TotalBytes[7:0] Byte 5 reserved B5_5 reserved DirectionPID[1:0] TotalBytes[9:8] Byte 6 Format FunctionAddress[6:0] Byte 7 reserved

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ISP1161A

Full-speed USB single-chip host and device controller

Table 5: Philips Transfer Descriptor (PTD): bit description

Symbol Access Description

ActualBytes[9:0] R/W Contains the number of bytes that were transferred for this PTD CompletionCode[3:0] R/W 0000 NoError General TD or isochronous data packet processing

completed with no detected errors. 0001 CRC Last data packet from endpoint contained a CRC error. 0010 BitStufﬁng Last data packet from endpoint contained a bit stufﬁng

violation. 0011 DataToggleMismatch Last packet from endpoint had data toggle PID that did

not match the expected value. 0100 Stall TD was moved to the Done queue because the

endpoint returned a STALL PID. 0101 DeviceNotResponding Device did not respond to token (IN) or did not provide a

handshake (OUT). 0110 PIDCheckFailure Check bits on PID from endpoint failed on data PID (IN)

or handshake (OUT) 0111 UnexpectedPID Received PID was not valid when encountered or PID

value is not deﬁned. 1000 DataOverrun The amount of data returned by the endpoint exceeded

either the size of the maximum data packet allowed

from the endpoint (foundinMaximumPacketSizeﬁeldof

ED) or the remaining buffer size. 1001 DataUnderrun The endpoint returned is less than MaximumPacketSize

and that amount was not sufﬁcient to ﬁll the speciﬁed

buffer. 1010 reserved 1011 reserved 1100 BufferOverrun During an IN, the HC received data from an endpoint

faster than it could be written to system memory. 1101 BufferUnderrun During an OUT, the HC could not retrieve data from the

system memory fast enough to keep up with the USB

data rate.

Active R/W Set to logic 1 by ﬁrmware to enable the execution of transactions by the HC. When the

transaction associated with this descriptor is completed, the HC sets this bit to logic 0, indicating that a transaction for this element will not be executed when it is next encountered in the schedule.

Toggle R/W Used to generate or compare the data PID value (DATA0 or DATA1). It is updated after

each successful transmission or reception of a data packet.

MaxPacketSize[9:0] R The maximum number of bytes that can be sent to or received from the endpoint in a

single data packet.

EndpointNumber[3:0] R USB address of the endpoint within the function. Last R Last PTD of a list (ITL or ATL). Logic 1 indicates that the PTD is the last PTD. Speed R Speed of the endpoint:

0 — full speed 1 — low speed

TotalBytes[9:0] R Speciﬁes the total number of bytes to be transferred with this data structure.ForBulk and

Control only, this can be greater than MaximumPacketSize.

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Full-speed USB single-chip host and device controller

Table 5: Philips Transfer Descriptor (PTD): bit description

Symbol Access Description

DirectionPID[1:0] R 00 SETUP

01 OUT 10 IN 11 reserved

B5_5 R/W This bit is logic 0 at power-on reset. When this feature is not used, software used for

ISP1161A is the same for ISP1160 and ISP1161. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only 1 PTD USB transaction will be sent out in 1 ms.

Format R The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then

Format = 0. If this is an Isochronous endpoint, then Format = 1.

FunctionAddress[6:0] R This is the USB address of the function containing the endpoint that this PTD refers to.

…continued

9.4 HC internal FIFO buffer RAM structure

9.4.1 Partitions

According to the USB data transfers: Control, Bulk, Interrupt and Isochronous.

The HC’s internal FIFO bufferRAM has a physical size of 4 kbytes. This internal FIFO buffer RAM is used for transferring data between the microprocessor and USB peripheral devices. This on-chip buffer RAM can be partitioned into two areas: Acknowledged Transfer List (ATL) buffer and Isochronous (ISO)Transfer List (ITL) buffer. The ITL buffer is a Ping-Pong structured FIFO buffer RAM that is used to keep the payload data and their PTD header for Isochronous transfers. The ATL buffer is a non Ping-Pong structured FIFO buffer RAM that is used for the other three types of transfers.

Universal Serial Bus Speciﬁcation Rev. 2.0

, there are four types of

The ITL buffer can be further partitioned into ITL0 and ITL1 for the Ping-Pong structure. The ITL0 buffer and ITL1 buffer always have the same size. The microprocessor can put ISO data into either the ITL0 buffer or the ITL1 buffer. When the microprocessor accesses an ITL buffer, the HC can take over the other ITL buffer at the same time. This architecture improves the ISO transfer performance.

The HCD can assign the logical size for the ATL bufferand ITL buffers at any time, but normally at initialization after power-on reset. This is done by setting the HcATLBufferLength register (2BH - read, ABH - write) and HcITLBufferLength register (2AH - read, AAH - write). The total buffer length cannot exceed the maximum RAM size of 4 kbytes (ATL buffer + ITL buffer). Figure 26 shows the partitions of the internal FIFO buffer RAM. When assigning buffer RAM sizes, follow this formula:

ATL buffer length + 2 × (ITL buffer size) ≤ 1000H (that is, 4 kbytes) where: ITL buffer size = ITL0 buffer length = ITL1 buffer length The following assignments are examples of legal uses of the internal FIFO buffer

RAM:

• ATL buffer length = 800H, ITL buffer length = 400H.

This is the maximum use of the internal FIFO buffer RAM.

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• ATL buffer length = 400H, ITL buffer length = 200H.

• ATL buffer length = 1000H, ITL buffer length = 0H.

ISP1161A

Full-speed USB single-chip host and device controller

This is insufﬁcient use of the internal FIFO buffer RAM.

This will use the internal FIFO buffer RAM for only ATL transfers.

FIFO buffer RAM

top

ITL0

ITL buffer

ITL1

ISO_A

ISO_B

programmable

sizes

ATL buffer

Fig 26. HC internal FIFO buffer RAM partitions.

ATL

bottom

control/bulk/interrupt

data

not used

MGT950

4 kbytes

The actual requirement for the buffer RAM need not reach the maximum size. You can make your selection based on your application. The following are some calculations of the ISO_A or ISO_B space for a frame of data:

• Maximum number of useful data sent during one USB frame is 1280 bytes (20

ISO packets of 64 bytes). The total RAM size needed is: 20 × 8 + 1280 = 1440 bytes.

• Maximum number of packets for different endpoints sent during one USB frame is

150 (150 ISO packets of 1 byte). The total RAM size needed is: 150 × 8 + 150 × 1 = 1350 bytes.

• The Ping buffer RAM (ITL0) and the Pong bufferRAM (ITL1) have a maximum size

of 2 kbytes each. All data needed for one frame can be stored in the Ping or the Pong buffer RAM.

When the embedded system wants to initiate a transfer to the USB bus, the data needed for one frame is transferred to the ATL buffer or ITL buffer. The microprocessor detects the buffer status through the interrupt routines. When the HcBufferStatus register (2CH - read only) indicates that the buffer is empty, then the microprocessor writes data into the buffer. When the HcBufferStatus register indicates that the buffer is full, the data is ready on the buffer,and the microprocessor needs to read data from the buffer.

During every 1 ms, there might be many events to generate interrupt requests to the microprocessor for data transfer or status retrieval. However, each of the interrupt types deﬁned in this speciﬁcation can be enabled or disabled by setting the HcµPInterruptEnable register bits accordingly.

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