Philips ISP1161A User Manual

ISP1161A

Full-speed Universal Serial Bus single-chip host and device controller

Rev. 03 — 23 December 2004 Product data

1. General description

The ISP1161A is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC). The Host Controller portion of the ISP1161A complies with

Universal Serial Bus Speciﬁcation Rev. 2.0

(12 Mbit/s) and low-speed (1.5 Mbit/s). The Device Controller portion of the ISP1161A also complies with data rates at full-speed (12 Mbit/s). These two USB controllers, the HC and the DC, share the same microprocessor bus interface. They have the same data bus, but different I/O locations. They also have separate interrupt request output pins, separate DMA channels that include separate DMA request output pins and DMA acknowledge input pins. This makes it possible for a microprocessor to control both the USB HC and the USB DC at the same time.

ISP1161A provides two downstream ports forthe USB HC and one upstream port for the USB DC. Each downstream port has an overcurrent (OC) detection input pin and power supply switching control output pin. The upstream port has a V input pin. ISP1161A also provides separate wake-up input pins and suspended status output pins for the USB HC and the USB DC, respectively. This makes power management ﬂexible. The downstream ports for the HC can be connected with any USB compliant devices and hubs that have USB upstream ports. The upstream port for the DC can be connected to any USB compliant USB host and USB hubs that have USB downstream ports.

, supporting data rates at full-speed

Universal Serial Bus Speciﬁcation Rev. 2.0

BUS

, supporting

detection

The HC is adapted from the

Release 1.0a

The DC is compliant with most USB device class speciﬁcations such as Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices and Human Interface Devices.

ISP1161A is well suited for embedded systems and portable devices that require a USB host only, a USB device only, or a combination of a conﬁgurable USB host and USB device. ISP1161A brings high ﬂexibility to the systems that have it built-in. For example, a system that uses an ISP1161A allows it not only to be connected to a PC or USB hub with a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse. Therefore, the ISP1161A enables peer-to-peer connectivity between embedded systems. An interesting application example is to connect an ISP1161A HC with an ISP1161A DC.

Consider an example of an ISP1161A being used in a Digital Still Camera (DSC) design. Figure 1 shows an ISP1161A being used as a USB DC. Figure 2 shows an ISP1161A being used as a USB HC. Figure 3 shows an ISP1161A being used as a USB HC and a USB DC at the same time.

, referred to as OHCI in the rest of this document.

Open Host Controller Interface Speciﬁcation for USB

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

EMBEDDED SYSTEM

(host)

USB I/F

Fig 1. ISP1161A operating as a USB device.

EMBEDDED SYSTEM

µP

ISP1161A

HOST/

DEVICE

DSC

USB cable

µP SYSTEM

MEMORY

µP bus I/F

USB host

USB I/F

µP

ISP1161A

USB device

USB cable

µP SYSTEM

MEMORY

µP bus I/F

HOST/

DEVICE

DSC

004aaa080

PRINTER

(device)

USB I/F

004aaa081

Fig 2. ISP1161A operating as a stand-alone USB host.

EMBEDDED SYSTEM

ISP1161A

HOST/

DEVICE

µP SYSTEM

MEMORY

µP bus I/F

USB host

PRINTER

(device)

USB I/FUSB I/F

USB I/F

004aaa082

(host)

µP

DSC

USB cable USB cable

USB I/F

USB device

Fig 3. ISP1161A operating as both USB host and device simultaneously.

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2. Features

ISP1161A

Full-speed USB single-chip host and device controller

■ Complies with

■ The Host Controller portion of the ISP1161A supports data transfer at full-speed

(12 Mbit/s) and low-speed (1.5 Mbit/s); the Device Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s)

■ Combines the HC and the DC in a single chip

■ On-chip DC complies with most USB device class speciﬁcations

■ Both the HC and the DC can be accessed by an external microprocessor via

separate I/O port addresses

■ Selectable one or two downstream ports for the HC and one upstream port for the

■ High-speed parallel interface to most of the generic microprocessors and

Reduced Instruction Set Computer (RISC) processors such as:

◆ Hitachi® SuperH™ SH-3 and SH-4

◆ MIPS-based™ RISC

◆ ARM7™, ARM9™, StrongARM

■ Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC,

11.1 Mbyte/s data transfer rate between the microprocessor and the DC

■ Supports single-cycle and burst mode DMA operations

■ Up to 14 programmable USB endpoints with 2 ﬁxed control IN/OUT endpoints for

the DC

■ Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes)

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer for both DC transfers and HC isochronous (ISO) transactions

■ 6 MHz crystal oscillator with integrated PLL for low EMI

■ Controllable LazyClock (100 kHz ± 50 %) output during ‘suspend’

■ Clock output with programmable frequency (3 MHz to 48 MHz)

■ Software controlled connection to the USB bus (SoftConnect™) on upstream port

for the DC

■ Good USB connection indicator that blinks with trafﬁc (GoodLink™) for the DC

■ Software selectable internal 15 kΩ pull-down resistors for HC downstream ports

■ Dedicated pins for suspend sensing output and wake-up control input for ﬂexible

applications

■ Global hardware reset input pin and separate internal software reset circuits for

HC and DC

■ Operation from a 5 V or a 3.3 V power supply

■ Operating temperature range −40 °Cto+85 °C

■ Available in two LQFP64 packages (SOT314-2 and SOT414-1).

Universal Serial Bus Speciﬁcation Rev. 2.0

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Philips Semiconductors

Full-speed USB single-chip host and device controller

ISP1161A

3. Applications

■ Personal Digital Assistant (PDA)

■ Digital camera

■ Third-generation (3-G) phone

■ Set-Top Box (STB)

■ Information Appliance (IA)

■ Photo printer

■ MP3 jukebox

■ Game console.

4. Ordering information

Table 1: Ordering information

Type number Package

Name Description Version

ISP1161ABD LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 ISP1161ABM LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 7 × 7 × 1.4 mm SOT414-1

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xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

6 MHz

5. Block diagram

Philips Semiconductors

to/from

microprocessor

H_WAKEUP

H_SUSPEND

NDP_SEL

D0 to D15

RD CS

A1 A0

DACK2 DACK1

EOT DREQ2 DREQ1

INT2 INT1

D_WAKEUP

D_SUSPEND

RESET

40 42 33 2 to 7,

9 to 14, 16, 17, 63, 64

RESET

AGND

ISP1161A

HOST BUS

INTERFACE

DEVICE BUS

INTERFACE

3.3 V

reg(3.3)

hold2

internal

reset

internal

supply

245857

hold1

22 21 23 60 59 28 27 34 26 25 30 29

37 36

DGND

HOST/

DEVICE

AUTOMUX

1, 8, 15, 18, 35, 45, 62

POWER-ON

VOLTAGE

REGULATOR

HOST CONTROLLER

ALT RAM

ITL0

(PING RAM)

PHILIPS SLAVE

HOST CONTROLLER

Host bus

Device bus

DEVICE

CONTROLLER

PING

PONG

RAM

DEVICE CONTROLLER

RAM

ITL1

(PONG RAM)

GoodLink

RECOVERY

CLOCK

PLL

CLOCK

PROGRAMMABLE

DIVIDER

413819

CLKOUT

XTAL1XTAL2 43

OVERCURRENT

TRANSCEIVER

SoftConnect

POWER

SWITCHING

DETECTION

USB

4×

15 kΩ

USB

n.c.

GND

1.5 kΩ

61, 20

3.3 V

46 47 54 55

50 51 52 53

39 48 49

004aaa083

H_PSW1 H_PSW2 H_OC1 H_OC2

H_DM1 H_DP1

H_DM2 H_DP2

D_VBUS D_DM D_DP

USB bus

downstream

ports

USB bus upstream

port

Full-speed USB single-chip host and device controller

ISP1161A

Fig 4. Block diagram.

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

POWER-ON

RESET

ITL0 RAM

MANAGEMENT

Host

bus I/F

µP interface

BUS I/F

DMA

HANDLER

µP

HANDLER

Fig 5. Host controller sub-block diagram.

POWER-ON

RESET

DMA HANDLER

Device

bus I/F

BUS I/F

µP HANDLER

ATL RAM

ITL1 RAM

MEMORY

UNIT

Host controller sub-blocks

MANAGEMENT UNIT

INTEGRATED

RAM

MEMORY

ACCESS

USB

STATE

FRAME

MANAGE-

MENT

PDT_LIST

PROCESS

PHILIPS SIE

SoftConnect

TRANSCEIVER

USB InterfacePhilips sHC coreMemory block

clock

recovery

PHILIPS

SIE

USB

TRANSCEIVER

3.3 V

USB

MGT930

USB bus

H_DP1 H_DM1 H_DP2 H_DM2

USB bus

D_DP D_DM

clock recovery

EP HANDLER

Device controller sub-blocks

GoodLink

MGT931

Fig 6. Device controller sub-block diagram.

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6. Pinning information

6.1 Pinning

ISP1161A

Full-speed USB single-chip host and device controller

DGND

D2 D3 D4 D5 D6 D7

DGND

D9 D10 D11 D12 D13

DGND

D14

DGND

n.c.A1A0

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

reg(3.3)

ISP1161ABD ISP1161ABM

AGND 57

VCCH_OC2 56

H_OC1 54

H_DP2 53

H_DM2 52

H_DP1 51

H_DM1 50

D_DP49

D_DM H_PSW2

H_PSW1

DGND

45 44

XTAL2

XTAL1

H_SUSPEND CLKOUT

41 40

H_WAKEUP

D_VBUS

GL D_WAKEUP

D_SUSPEND

DGND

EOT

NDP_SEL

D15

DGND

hold1

20 n.c.

22 RD

23 WR

hold2

DREQ1

DACK1

DREQ2

DACK2

INT1

INT2

TEST

004aaa085

RESET

Fig 7. Pin conﬁguration LQFP64.

6.2 Pin description

Table 2: Pin description for LQFP64

Symbol

DGND 1 - digital ground D2 2 I/O bit 2 of bidirectional data; slew-rate controlled; TTL input;

D3 3 I/O bit 3 of bidirectional data; slew-rate controlled; TTL input;

D4 4 I/O bit 4 of bidirectional data; slew-rate controlled; TTL input;

D5 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input;

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[1]

Pin Type Description

three-state output

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

Table 2: Pin description for LQFP64

Symbol

[1]

Pin Type Description

…continued

D6 6 I/O bit 6 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D7 7 I/O bit 7 of bidirectional data; slew-rate controlled; TTL input;

three-state output DGND 8 - digital ground D8 9 I/O bit 8 of bidirectional data; slew-rate controlled; TTL input;

three-state output D9 10 I/O bit 9 of bidirectional data; slew-rate controlled; TTL input;

three-state output D10 11 I/O bit 10 of bidirectional data; slew-rate controlled; TTL input;

three-state output D11 12 I/O bit 11 of bidirectional data; slew-rate controlled; TTL input;

three-state output D12 13 I/O bit 12 of bidirectional data; slew-rate controlled; TTL input;

three-state output D13 14 I/O bit 13 of bidirectional data; slew-rate controlled; TTL input;

three-state output DGND 15 - digital ground D14 16 I/O bit 14 of bidirectional data; slew-rate controlled; TTL input;

three-state output D15 17 I/O bit 15 of bidirectional data; slew-rate controlled; TTL input;

three-state output DGND 18 - digital ground V

hold1

19 - voltage holding pin; internallyconnected to the V

pins. When VCC is connected to 5 V, this pin will

hold2

output 3.3 V, hence do not connect it to 5 V. When V

reg(3.3)

and

connected to 3.3 V, this pin can either be connected to

3.3 V or left unconnected. In all cases, decouple this pin to

DGND. n.c. 20 - no connection CS 21 I chip select input RD 22 I read strobe input WR 23 I write strobe input V

hold2

24 - voltage holding pin; internallyconnected to the V

pins. When VCC is connected to 5 V, this pin will

hold1

output 3.3 V, hence do not connect it to 5 V. When V

reg(3.3)

and

connected to 3.3 V, this pin can either be connected to

3.3 V or left unconnected. In all cases, decouple this pin to

DGND. DREQ1 25 O HC DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161A wants to start a

DMA transfer; see Section 10.4.1 DREQ2 26 O DC DMA request output (programmable polarity); signals

to the DMA controller that the ISP1161A wants to start a

DMA transfer; see Section 13.1.4 DACK1 27 I HC DMA acknowledgeinput; when not in use,this pin must

be connected to V

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via an external 10 kΩ resistor

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

Table 2: Pin description for LQFP64

Symbol

[1]

Pin Type Description

…continued

DACK2 28 I DC DMA acknowledgeinput; when not in use,this pin must

be connected to V

via an external 10 kΩ resistor

INT1 29 O HC interrupt output; programmable level, edge triggered

and polarity; see Section 10.4.1 INT2 30 O DC interrupt output; programmable level, edge triggered

and polarity; see Section 13.1.4 TEST 31 O test output; used for test purposes only; this pin is not

connected during normal operation RESET 32 I reset input (Schmitt trigger); a LOW level produces an

asynchronous reset (internal pull-up resistor) NDP_SEL 33 I indicates to the HC software the Number of Downstream

Ports (NDP) present:

0 — select 1 downstream port

1 — select 2 downstream ports

only changes the value of the NDP ﬁeld in the

HcRhDescriptorA register; both ports will always be

enabled; see Section 10.3.1

(internal pull-up resistor) EOT 34 I DMA master device to inform the ISP1161A of end of DMA

transfer; active level is programmable; see Section 10.4.1 DGND 35 - digital ground D_SUSPEND 36 O DC ‘suspend’ state indicator output; active HIGH D_WAKEUP 37 I DC wake-up input; generates a remote wake-up from

‘suspend’ state (active HIGH); when not in use, this pin

must be connected to DGND via an external 10 kΩ resistor

(internal pull-down resistor) GL 38 O GoodLink LED indicator output (open-drain, 8 mA); the

LED is default ON, blinks OFF upon USB trafﬁc; to connect

a LED use a series resistor of 470 Ω (V

330 Ω (V

= 3.3 V)

D_VBUS 39 I DC USB upstream port V

sensing input; when not in

BUS

= 5.0 V) or

use, this pin must be connected to DGND via a 1 MΩ

resistor H_WAKEUP 40 I HC wake-up input; generates a remote wake-up from

‘suspend’ state (active HIGH); when not in use, this pin

must be connected to DGND via an external 10 kΩ resistor

(internal pull-down resistor) CLKOUT 41 O programmable clock output (3 MHz to 48 MHz); default

12 MHz H_SUSPEND 42 O HC ‘suspend’ state indicator output; active HIGH XTAL1 43 I crystal input; connected directly to a 6 MHz crystal; when

XTAL1 is connected to an external clock source, pin XTAL2

must be left open XTAL2 44 O crystal output; connected directly to a 6 MHz crystal; when

pin XTAL1 is connected to an external clock source, this

pin must be left open

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ISP1161A

Full-speed USB single-chip host and device controller

Table 2: Pin description for LQFP64

Symbol

[1]

Pin Type Description

…continued

DGND 45 - digital ground H_PSW1 46 O power switching control output for downstream port 1;

open-drain output H_PSW2 47 O power switching control output for downstream port 2;

open-drain output D_DM 48 AI/O USB D− data line for DC upstream port; when not in use,

this pin must be left open D_DP 49 AI/O USB D+ data line for DC upstream port; when not in use,

this pin must be left open H_DM1 50 AI/O USB D− data line for HC downstream port 1 H_DP1 51 AI/O USB D+ data line for HC downstream port 1 H_DM2 52 AI/O USB D− data line for HC downstream port 2; when not in

use, this pin must be left open H_DP2 53 AI/O USB D+ data line for HC downstream port 2; when not in

use, this pin must be left open H_OC1 54 I overcurrent sensing input for HC downstream port 1 H_OC2 55 I overcurrent sensing input for HC downstream port 2 V

56 - power supply voltage input (3.0 V to 3.6 V or

4.75 V to 5.25 V). This pin connects to the internal 3.3 V

regulator input. When connected to 5 V, the internal

regulator will output 3.3 V to pins V

reg(3.3),Vhold1

and V

hold2

When connected to 3.3 V, it will bypass the internal

regulator. AGND 57 - analog ground V

reg(3.3)

58 - internal 3.3 V regulator output; when the VCC pin is

connected to 5 V, this pin outputs 3.3 V. When the V

is connected to 3.3 V, connect this pin to 3.3 V. A0 59 I address input; selects command (A0 = 1) or data (A0 = 0) A1 60 I address input; selects AutoMux switching to DC (A1 = 1) or

AutoMux switching to HC (A1 = 0); see Table 3 n.c. 61 - no connection DGND 62 - digital ground D0 63 I/O bit 0 of bidirectional data; slew-rate controlled; TTL input;

three-state output D1 64 I/O bit 1 of bidirectional data; slew-rate controlled; TTL input;

three-state output

[1] Symbol names with an overscore (e.g. NAME) represent active LOW signals.

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7. Functional description

7.1 PLL clock multiplier

A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL.

7.2 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4 times over-sampling principle. It is able to track jitter and frequency drift as speciﬁed in the

7.3 Analog transceivers

Three sets of transceivers are embedded in the chip: two are used for downstream ports with USB connector type A; one is used for upstream port with USB connector type B. The integrated transceivers are compliant with the

Speciﬁcation Rev. 2.0

through external termination resistors.

ISP1161A

Full-speed USB single-chip host and device controller

Universal Serial Bus Speciﬁcation Rev. 2.0

. They interface directly with the USB connectors and cables

Universal Serial Bus

7.4 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no ﬁrmware intervention. The functions of this block include: synchronization pattern recognition, parallel to serial conversion, bit (de)stufﬁng, CRC checking and generation, Packet IDentiﬁer (PID) veriﬁcation and generation, address recognition, handshake evaluation and generation. There are separate SIEs in both the HC and the DC.

7.5 SoftConnect

The connection to the USB is accomplished by bringing D+ (for full-speed USB devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1161A DC, the 1.5 kΩ pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external or system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB. Re-initialization of the USB connection can also be performed without disconnecting the cable.

The ISP1161A DC will check for USB V established. V

Remark: The tolerance of the internal resistors is 25 %. This is higher than the 5 % tolerance speciﬁed by the USB speciﬁcation. However, the overall voltage speciﬁcation for the connection can still be met with a good margin. The decision to make use of this feature lies with the USB equipment designer.

sensing is provided through pin D_VBUS.

BUS

availability before the connection can be

BUS

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7.6 GoodLink

Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration, the LED indicator will blink on momentarily. When the DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161A the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off.

This feature provides a user-friendly indication of the status of the USB device, the connected hub and the USB trafﬁc. It is a useful ﬁeld diagnostics tool for isolating faulty equipment. It can therefore help to reduce ﬁeld support and hotline overhead.

8. Microprocessor bus interface

8.1 Programmed I/O (PIO) addressing mode

A generic PIO interface is deﬁned for speed and ease-of-use. It also allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1161A appears as a memory device with a 16-bit data bus and uses only two address lines: A1 and A0 to access the internal control registers and FIFO buffer RAM. Therefore, the ISP1161A occupies only four I/O ports or four memory locations of a microprocessor. External microprocessors can read from or write to the ISP1161A internal control registers and FIFO bufferRAM through the Programmed I/O (PIO) operating mode. Figure 8 shows the Programmed I/O interface between a microprocessor and an ISP1161A.

ISP1161A

Full-speed USB single-chip host and device controller

MICRO-

PROCESSOR

D[15:0

IRQ1 IRQ2

µP bus I/F

]

A2 A1

D[15:0

RD WR CS A1 A0

INT1 INT2

]

ISP1161A

004aaa086

Fig 8. Programmed I/O interface between a microprocessor and an ISP1161A.

8.2 DMA mode

The ISP1161A also provides DMA mode for external microprocessors to access its internal FIFO buffer RAM. Data can be transferred by DMA operation between a microprocessor’s system memory and the ISP1161A internal FIFO buffer RAM.

Remark: The DMA operation must be controlled by the external microprocessor system DMA controller (Master).

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Figure 9 shows the DMA interface between a microprocessor system and the

ISP1161A. The ISP1161A provides two DMA channels:

• DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer

• DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer

The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1161A provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConﬁguration register (21H - read, A1H - write) enables the ISP1161A HC internal DMA counter for DMA transfer. When the DMA counter reaches the value set in the HcTransferCounter register (22H - read, A2H - write), an internal EOT signal will be generated to terminate the DMA transfer.

ISP1161A

Full-speed USB single-chip host and device controller

between a microprocessor’s system memory and ISP1161A HC internal FIFO buffer RAM

between a microprocessor system memory and the ISP1161A DC internal FIFO buffer RAM.

µP bus I/F

]

D[15:0

MICRO-

PROCESSOR

DACK1

DREQ1

DACK2

DREQ2

EOT

Fig 9. DMA interface between a microprocessor and an ISP1161A.

8.3 Control register access by PIO mode

8.3.1 I/O port addressing

Table 3 shows the ISP1161A I/O port addressing. Complete decoding of the I/O port

address should include the chip select signal CS and the address lines A1 and A0. However, the direction of the access of the I/O ports is controlled by the RD and WR signals. When RD is LOW, the microprocessor reads data from the ISP1161A data port. When WR is LOW, the microprocessor writes a command to the command port, or writes data to the data port.

D[15:0

RD WR

DACK1 DREQ1

DACK2 DREQ2

EOT

]

ISP1161A

004aaa087

Table 3: I/O port addressing

Port Pin CS Pin A1 Pin A0 Access Data bus width Description

0 LOW LOW LOW R/W 16 bits HC data port 1 LOW LOW HIGH W 16 bits HC command port 2 LOW HIGH LOW R/W 16 bits DC data port 3 LOW HIGH HIGH W 16 bits DC command port

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Figure 10 and Figure 11 illustrate how an external microprocessor accesses the

ISP1161A internal control registers.

Fig 10. A microprocessor accessing an HC or a DC via an automux switch.

Full-speed USB single-chip host and device controller

AUTOMUX

DC/HC

µP bus I/F

When A1 = 0, the microprocessor accesses the HC. When A1 = 1, the microprocessor accesses the DC.

CMD/DATA

SWITCH

command port

Host or Device

bus I/F

data port

Host bus I/F

Device bus I/F

MGT935

ISP1161A

Commands

Command register

When A0 = 0, the microprocessor accesses the data port. When A0 = 1, the microprocessor accesses the command port.

Fig 11. A microprocessor accessing internal control registers.

8.3.2 Register access phases

The ISP1161A register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1161A to the next register to be accessed. A command is 8 bits long. On a microprocessor’s 16-bit data bus, a command occupies the lower byte, with the upper byte ﬁlled with zeros.

Figure 12 shows a complete 16-bit register access cycle for the ISP1161A. The

microprocessor writes a command code to the command port, and then reads or writes the data word from or to the data port. Take the example of a microprocessor attempting to read the ISP1161A’s ID. The ID is kept in the HC’s HcChipID register (index 27H, read only). The 16-bit register access cycle is therefore:

1. Microprocessor writes the command code of 27H (0027H in 16-bit width) to the HC command port

2. Microprocessor reads the data word of the chip’s ID from the HC data port.

Control registers

MGT936

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ISP1161A

Full-speed USB single-chip host and device controller

16-bit register access cycle

write command

(16 bits)

read/write data

(16 bits)

MGT937

Fig 12. 16-bit register access cycle.

Most of the ISP1161A internal control registers are 16 bits wide. Some of the internal control registers have 32-bit width. Figure 13 shows how the 32-bit internal control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor ﬁrst reads or writes the lower 16-bits, followed by the upper 16-bits.

32-bit register access cycle

write command

(16 bits)

read/write data

(lower 16 bits)

read/write data

(upper 16 bits)

MGT938

Fig 13. 32-bit register access cycle.

To further describe the complete access cycles of the internal control registers, the status of some pins of the microprocessor bus interface are shown in Figure 14 and

Figure 15 for the HC and the DC respectively.

A1, A0

D[15:0

]

01 00 00

HC command

code

Fig 14. Accessing HC control registers.

HC register data

(lower word)

readread

writewritewrite

writewrite

readread

HC register data

(upper word)

MGT939

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ISP1161A

Full-speed USB single-chip host and device controller

A1, A0

D[15:0

]

11 10 10

DC command

code

DC register data

(lower word)

readread

writewritewrite

writewrite

readread

DC register data

(upper word)

Fig 15. Accessing DC control registers.

8.4 FIFO buffer RAM access by PIO mode

Since the ISP1161A internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register ﬁelds. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases.

FIFO buffer RAM access cycle (transfer counter = 2N)

MGT940

write command

(16 bits)

read/write data

#1 (16 bits)

Fig 16. Internal FIFO buffer RAM access cycle.

Figure 16 shows a complete access cycle of the HC internal FIFO buffer RAM. For a

write cycle, the microprocessor ﬁrst writes the FIFO buffer RAM’s command code to the command port, and then writes the data words one by one to the data port until half of the transfer’s byte count is reached. The HcTransferCounter register (22H read, A2H - write) is used to specify the byte count of a FIFO buffer RAM’s read cycle or write cycle. Every access cycle must be in the same access direction. The read cycle procedure is similar to the write cycle.

For access to the DC FIFO buffer RAM access, see Section 13.

read/write data

#2 (16 bits)

read/write data

#N (16 bits)

MGT941

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8.5 FIFO buffer RAM access by DMA mode

The DMA interface between a microprocessor and the ISP1161A is shown in

Figure 9.

When doing a DMA transfer, at the beginning of every burst the ISP1161A outputs a DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for DC). After receiving this signal, the microprocessor will reply with a DMA acknowledge via the DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA transfer through the data bus. In the DMA mode, the microprocessor must issue a read or write signal to the ISP1161A RD or WR pin. The ISP1161A will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer.

ISP1161A supports both external and internal EOT signals. The external EOT signal is received as input on pin EOT, and generally comes from the external microprocessor. The internal EOT signal is generated by the ISP1161A internally.

To select either EOT method, set the appropriate DMA conﬁguration register (see

Section 10.4.2 and Section 13.1.6). For example, for the HC, setting

DMACounterSelect bit of the HcDMAConﬁguration register (21H - read, A1H - write) to logic 1 will enable the DMA counter for DMA transfer. When the DMA counter reaches the value of the HcTransferCounter register, the internal EOT signal will be generated to terminate the DMA transfer.

ISP1161A

Full-speed USB single-chip host and device controller

ISP1161A supports either single-cycle DMA operation or burst mode DMA operation.

DREQ

DACK

RD or WR

]

D[15:0

data #1 data #2 data #N

EOT

004aaa103

N = 1/2 byte count of transfer data.

Fig 17. DMA transfer in single-cycle mode.

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DREQ

DACK

RD or WR

]

D[15:0

data #1 data #K data #2K data #Ndata #(K+1) data #(N−K+1)

EOT

N = 1/2 byte count of transfer data, K = number of cycles/burst.

Fig 18. DMA transfer in burst mode.

In Figure 17 and Figure 18, the hardware is conﬁgured such that DREQ is active HIGH and DACK is active LOW.

ISP1161A

Full-speed USB single-chip host and device controller

004aaa104

8.6 Interrupts

The ISP1161A has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2).

8.6.1 Pin conﬁguration

The interrupt output signals have four conﬁguration modes: Mode 0 Level trigger, active LOW (default at power-up)

Mode 1 Level trigger, active HIGH Mode 2 Edge trigger, active LOW Mode 3 Edge trigger, active HIGH.

Figure 19 shows these four interrupt conﬁguration modes. They are programmable

via the HcHardwareConﬁguration register (see Section 10.4.1), which are also used to disable or enable the signals.

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Full-speed USB single-chip host and device controller

INT

Mode 0 level triggered, active LOW

INT

Mode 1 level triggered, active HIGH

INT

Mode 2 edge triggered, active LOW

INT

Mode 3 edge triggered, active HIGH

Fig 19. Interrupt pin operating modes.

8.6.2 HC’s interrupt output pin (INT1)

To program the four conﬁguration modes of the HC’s interrupt output signal (INT1), set bits InterruptPinTrigger and InterruptOutputPolarity of the HcHardwareConﬁguration register (20H - read, A0H - write). Bit InterruptPinEnableis used as the master enable setting for pin INT1.

INT active

166 ns

INT active

166 ns

clear or disable INT

MGT944

INT1 has many associated interrupt events, as shown as in Figure 20. The interrupt events of the HcµPInterrupt register (24H - read, A4H - write) changes

the status of pin INT1 when the corresponding bits of the HcµPInterruptEnable register (25H - read, A5H - write) and pin INT1’s global enable bit (InterruptPinEnable of the HcHardwareConﬁguration register) are all set to enable status.

However, events that come from the HcInterruptStatus register (03H - read, 83H write) affect only the OPR_Reg bit of the HcµPInterrupt register. They cannot directly change the status of pin INT1.

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ISP1161A

Full-speed USB single-chip host and device controller

HcInterruptEnable

MIE

RHSC

FNO

UE RD SF SO

RHSC

FNO

UE RD SF SO

HcInterruptStatus

group 2

HcµPInterrupt

ATLInt

SOFITLInt

AllEOTInterrupt

INT1

OPR_Reg

HCSuspended

group 1

ClkReady

LATCH

HcµPInterruptEnable

SOFITLInt

ATLInt

AllEOTInterrupt

HcHardwareConfiguration

InterruptPinEnable

OPR_Reg

HCSuspended

ClkReady

MGT945

Fig 20. HC interrupt logic.

There are two groups of interrupts represented by group 1 and group 2 in Figure 20. A pair of registers control each group.

Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus register). On occurrence of any of these events, the corresponding bit would be set to logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1, the 6-input OR gate would output logic 1. This output is ANDed with the value of MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause bit OPR in the HcµPInterrupt register to be set to logic 1.

Group 1 contains six possible interrupt events, one of which is the output of group 2 interrupt sources. The HcµPInterrupt and HcµPInterruptEnable registers work in the same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt group 2. The output from the 6-input OR gate is connected to a latch, which is controlled by InterruptPinEnable (bit 0 of the HcHardwareConﬁguration register).

In the eventin which the software wishes to temporarily disable the interrupt output of the ISP1161A Host Controller, the following procedure should be followed:

1. Make sure that bit InterruptPinEnable in the HcHardwareConﬁguration register is set to logic 1.

2. Clear all bits in the HcµPInterrupt register.

3. Set bit InterruptPinEnable to logic 0.

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To re-enable the interrupt generation:

1. Set all bits in the HcµPInterrupt register.

2. Set bit InterruptPinEnable to logic 1.

Remark: Bit InterruptPinEnable in the HcHardwareConﬁguration register latches the interrupt output. When this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operations on the interrupt control registers.

If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal without clearing the HcµPInterrupt register, the following procedure should be followed:

1. Make sure that bit InterruptPinEnable is set to logic 1.

2. Clear all bits in the HcµPInterruptEnable register.

3. Set bit InterruptPinEnable to logic 0.

To re-enable the interrupt generation:

1. Set all bits in the HcµPInterruptEnable register according to the HCD

2. Set bit InterruptPinEnable to logic 1.

ISP1161A

Full-speed USB single-chip host and device controller

requirements.

8.6.3 DC interrupt output pin (INT2)

The four conﬁguration modes of DC’s interrupt output pin INT2 can also be programmed by setting bits INTPOL and INTLVL of the DcHardwareConﬁguration register (BBH - read, BAH - write). Bit INTENA of the DcMode register (B9H - read, B8H - write)is used to enable pin INT2. Figure 21 shows the relationship between the interrupt events and pin INT2.

Each of the indicated USB events is logged in a status bit of the DcInterrupt register. Corresponding bits in the Interrupt Enable register determine whether or not an event will generate an interrupt.

Interrupts can be masked globally by means of the INTENA bit of the DcMode register (see Table 81).

The active level and signalling mode of the INT output is controlled by the INTPOL and INTLVL bits of the DcHardwareConﬁguration register (see Table 83). Default settings after reset are active LOW and level mode. When pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1.

Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the DcInterrupt register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated DcEndpointStatus register.

Bit BUSTATUS follows the USB bus status exactly, allowing the ﬁrmware to get the current bus status when reading the DcInterrupt register.

SETUP and OUT token interrupts are generated after the DC has acknowledged the associated data packet. In bulk transfer mode, the DC will issue interrupts for every ACK received for an OUT token or transmitted for an IN token.

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In isochronous mode, an interrupt is issued upon each packet transaction. The ﬁrmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt Enable register. If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows the ﬁrmware to keep data transfer synchronized with the host. After 3 missed SOF events, the DC will enter ‘suspend’ state.

An alternative way of handling isochronous data transfer is to enable both the SOF and the PSOF interrupts and disable the interrupt for each isochronous endpoint.

DcInterrupt register

RESET

SUSPND

RESUME

EP14

EP0IN

EP0OUT

IERST

IESUSP

IERESM

IESOF

IEP14

IEP0IN

IEP0OUT

IEEOT

DcInterruptEnable register

SOF

...

EOT

...

MGT946

ISP1161A

Full-speed USB single-chip host and device controller

. .

DcMode register

INTENA

LATCH

INT2

Fig 21. DC interrupt logic.

Interrupt control: Bit INTENA in the DcMode register is a global enable/disable bit.

The behavior of this bit is given in Figure 22.

INT2 pin

INTENA = 0

(during this time,

an interrupt event

occurs. For example,

SOF asserted.)

Pin INT2: HIGH = de-assert; LOW= assert (individual interrupts are enabled).

Fig 22. Behavior of bit INTENA.

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INTENA = 1

SOF asserted

INTENA = 0

SOF asserted

004aaa198

Philips Semiconductors

Event A (see Figure 22): When an interrupt eventoccurs (for example, SOF interrupt) with bit INTENA set to logic 0, an interrupt will not be generated at pin INT2. However, it will be registered in the corresponding DcInterrupt register bit.

Event B (see Figure 22): When bit INTENA is set to logic 1, pin INT2 is asserted because bit SOF in the DcInterrupt register is already asserted.

Event C (see Figure 22): If the ﬁrmware sets bit INTENA to logic 0, pin INT2 will still be asserted. The bold dashed line shows the desired behavior of pin INT2.

De-assertion of pin INT2 can be achieved in the following manner. Bits[23:8] of the DcInterrupt register are endpoint interrupts. These interrupts are cleared on reading their respective DcEndpointStatus register. Bits[7:0] of the DcInterrupt register are bus status and EOT interrupts that are cleared on reading the DcInterrupt register. Make sure that bit INTENA is set to logic 1 when you perform the clear interrupt commands.

For more information on interrupt control, see Section 13.1.3, Section 13.1.5 and

Section 13.3.6.

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Full-speed USB single-chip host and device controller

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9. USB host controller (HC)

9.1 HC’s four USB states

The ISP1161A USB HC has four USB states − USBOperational, USBReset, USBSuspend, and USBResume − that deﬁne the HC’s USB signaling and bus states responsibilities.

ISP1161A

Full-speed USB single-chip host and device controller

USBOperational write

USBSuspend write

Fig 23. ISP1161A HC USB states.

The USB states are reﬂected in the HostControllerFunctionalState ﬁeld of the HcControl register (01H - read, 81H - write), which is located at bits 7 and 6 of the register.

USBOperational

USBSuspend

USBOperational write

USBResume

USBResume write

remote wake-up

USBReset write

USBReset

hardware or software

reset

USBReset write

MGT947

The Host Controller Driver (HCD) can perform only the USB state transitions shown in Figure 23.

Remark: The Software Reset in Figure 23 is not caused by the HcSoftwareReset command. It is caused by the HostControllerReset ﬁeld of the HcCommandStatus register (02H - read, 82H - write).

9.2 Generating USB trafﬁc

USB trafﬁc can be generated only when the ISP1161A USB HC is in the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState ﬁeld of the HcControl register before generating USB trafﬁc.

A simplistic ﬂow diagram showing when and how to generate USB trafﬁc is shown in

Figure 24. For more detail, refer to the

protocol and ISP1161A USB HC register usage.

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USB Speciﬁcation Revision 2.0

about the

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

Reset

HC state =

Initialize

Entry

USBOperational

USB traffic?

HC informs HCD of

USB traffic results

Fig 24. ISP1161A HC USB transaction loop

The USB trafﬁc blocks are:

• Reset

This includes hardware reset by pin RESET and software reset by the HcSoftwareReset command (A9H). The reset function will clear all the HC’s internal control registers to their reset status. After reset, the HCD must initialize the ISP1161A USB HC by setting some registers.

• Initialize HC

It includes:

– Setting the physical size for the HC’s internal FIFO buffer RAM by setting the

HcITLBufferLength register (2AH - read, AAH - write) and the HcATLBufferLength register (2BH - read, ABH - write)

– Setting the HcHardwareConﬁguration register according to requirements – Clearing interrupt events, if required – Enabling interrupt events, if required – Setting the HcFmInterval register (0DH - read, 8DH - write) – Setting the HC’s Root Hub registers – Setting the HcControl register to move the HC into USBOperational state

9.3 PTD data structure

The Philips Transfer Descriptor (PTD) data structure provides communication between the HCD and the ISP1161A USB HC. The PTD data contains information required by the USB trafﬁc. PTD data consists of a PTD followed by its payload data, as shown in Figure 25.

top

bottom

Fig 25. PTD data in FIFO buffer RAM.

FIFO buffer RAM

PTD

payload data

PTD

payload data

PTD

payload data

PTD data #1

PTD data #2

PTD data #N

MGT949

The PTD data structure is used by the HC to deﬁne a buffer of data that will be moved to or from an endpoint in the USB device. This data buffer is set up for the current frame (1 ms frame) by the HCD. The payload data forevery transferin the frame must have a PTD as a header to describe the characteristics of the transfer. PTD data is DWORD aligned.

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ISP1161A

Full-speed USB single-chip host and device controller

9.3.1 PTD data header deﬁnition

The PTD forms the header of the PTD data. It tells the HC the transfer type, where the payload data goes, and the payload data’s actual size. A PTD is an 8 byte data structure that is very important for HCD programming.

Table 4: Philips Transfer Descriptor (PTD): bit allocation

Bit 7 6 5 4 3 2 1 0 Byte 0 ActualBytes[7:0] Byte 1 CompletionCode[3:0] Active Toggle ActualBytes[9:8] Byte 2 MaxPacketSize[7:0] Byte 3 EndpointNumber[3:0] Last Speed MaxPacketSize[9:8] Byte 4 TotalBytes[7:0] Byte 5 reserved B5_5 reserved DirectionPID[1:0] TotalBytes[9:8] Byte 6 Format FunctionAddress[6:0] Byte 7 reserved

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ISP1161A

Full-speed USB single-chip host and device controller

Table 5: Philips Transfer Descriptor (PTD): bit description

Symbol Access Description

ActualBytes[9:0] R/W Contains the number of bytes that were transferred for this PTD CompletionCode[3:0] R/W 0000 NoError General TD or isochronous data packet processing

completed with no detected errors. 0001 CRC Last data packet from endpoint contained a CRC error. 0010 BitStufﬁng Last data packet from endpoint contained a bit stufﬁng

violation. 0011 DataToggleMismatch Last packet from endpoint had data toggle PID that did

not match the expected value. 0100 Stall TD was moved to the Done queue because the

endpoint returned a STALL PID. 0101 DeviceNotResponding Device did not respond to token (IN) or did not provide a

handshake (OUT). 0110 PIDCheckFailure Check bits on PID from endpoint failed on data PID (IN)

or handshake (OUT) 0111 UnexpectedPID Received PID was not valid when encountered or PID

value is not deﬁned. 1000 DataOverrun The amount of data returned by the endpoint exceeded

either the size of the maximum data packet allowed

from the endpoint (foundinMaximumPacketSizeﬁeldof

ED) or the remaining buffer size. 1001 DataUnderrun The endpoint returned is less than MaximumPacketSize

and that amount was not sufﬁcient to ﬁll the speciﬁed

buffer. 1010 reserved 1011 reserved 1100 BufferOverrun During an IN, the HC received data from an endpoint

faster than it could be written to system memory. 1101 BufferUnderrun During an OUT, the HC could not retrieve data from the

system memory fast enough to keep up with the USB

data rate.

Active R/W Set to logic 1 by ﬁrmware to enable the execution of transactions by the HC. When the

transaction associated with this descriptor is completed, the HC sets this bit to logic 0, indicating that a transaction for this element will not be executed when it is next encountered in the schedule.

Toggle R/W Used to generate or compare the data PID value (DATA0 or DATA1). It is updated after

each successful transmission or reception of a data packet.

MaxPacketSize[9:0] R The maximum number of bytes that can be sent to or received from the endpoint in a

single data packet.

EndpointNumber[3:0] R USB address of the endpoint within the function. Last R Last PTD of a list (ITL or ATL). Logic 1 indicates that the PTD is the last PTD. Speed R Speed of the endpoint:

0 — full speed 1 — low speed

TotalBytes[9:0] R Speciﬁes the total number of bytes to be transferred with this data structure.ForBulk and

Control only, this can be greater than MaximumPacketSize.

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Full-speed USB single-chip host and device controller

Table 5: Philips Transfer Descriptor (PTD): bit description

Symbol Access Description

DirectionPID[1:0] R 00 SETUP

01 OUT 10 IN 11 reserved

B5_5 R/W This bit is logic 0 at power-on reset. When this feature is not used, software used for

ISP1161A is the same for ISP1160 and ISP1161. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only 1 PTD USB transaction will be sent out in 1 ms.

Format R The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then

Format = 0. If this is an Isochronous endpoint, then Format = 1.

FunctionAddress[6:0] R This is the USB address of the function containing the endpoint that this PTD refers to.

…continued

9.4 HC internal FIFO buffer RAM structure

9.4.1 Partitions

According to the USB data transfers: Control, Bulk, Interrupt and Isochronous.

The HC’s internal FIFO bufferRAM has a physical size of 4 kbytes. This internal FIFO buffer RAM is used for transferring data between the microprocessor and USB peripheral devices. This on-chip buffer RAM can be partitioned into two areas: Acknowledged Transfer List (ATL) buffer and Isochronous (ISO)Transfer List (ITL) buffer. The ITL buffer is a Ping-Pong structured FIFO buffer RAM that is used to keep the payload data and their PTD header for Isochronous transfers. The ATL buffer is a non Ping-Pong structured FIFO buffer RAM that is used for the other three types of transfers.

Universal Serial Bus Speciﬁcation Rev. 2.0

, there are four types of

The ITL buffer can be further partitioned into ITL0 and ITL1 for the Ping-Pong structure. The ITL0 buffer and ITL1 buffer always have the same size. The microprocessor can put ISO data into either the ITL0 buffer or the ITL1 buffer. When the microprocessor accesses an ITL buffer, the HC can take over the other ITL buffer at the same time. This architecture improves the ISO transfer performance.

The HCD can assign the logical size for the ATL bufferand ITL buffers at any time, but normally at initialization after power-on reset. This is done by setting the HcATLBufferLength register (2BH - read, ABH - write) and HcITLBufferLength register (2AH - read, AAH - write). The total buffer length cannot exceed the maximum RAM size of 4 kbytes (ATL buffer + ITL buffer). Figure 26 shows the partitions of the internal FIFO buffer RAM. When assigning buffer RAM sizes, follow this formula:

ATL buffer length + 2 × (ITL buffer size) ≤ 1000H (that is, 4 kbytes) where: ITL buffer size = ITL0 buffer length = ITL1 buffer length The following assignments are examples of legal uses of the internal FIFO buffer

RAM:

• ATL buffer length = 800H, ITL buffer length = 400H.

This is the maximum use of the internal FIFO buffer RAM.

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• ATL buffer length = 400H, ITL buffer length = 200H.

• ATL buffer length = 1000H, ITL buffer length = 0H.

ISP1161A

Full-speed USB single-chip host and device controller

This is insufﬁcient use of the internal FIFO buffer RAM.

This will use the internal FIFO buffer RAM for only ATL transfers.

FIFO buffer RAM

top

ITL0

ITL buffer

ITL1

ISO_A

ISO_B

programmable

sizes

ATL buffer

Fig 26. HC internal FIFO buffer RAM partitions.

ATL

bottom

control/bulk/interrupt

data

not used

MGT950

4 kbytes

The actual requirement for the buffer RAM need not reach the maximum size. You can make your selection based on your application. The following are some calculations of the ISO_A or ISO_B space for a frame of data:

• Maximum number of useful data sent during one USB frame is 1280 bytes (20

ISO packets of 64 bytes). The total RAM size needed is: 20 × 8 + 1280 = 1440 bytes.

• Maximum number of packets for different endpoints sent during one USB frame is

150 (150 ISO packets of 1 byte). The total RAM size needed is: 150 × 8 + 150 × 1 = 1350 bytes.

• The Ping buffer RAM (ITL0) and the Pong bufferRAM (ITL1) have a maximum size

of 2 kbytes each. All data needed for one frame can be stored in the Ping or the Pong buffer RAM.

When the embedded system wants to initiate a transfer to the USB bus, the data needed for one frame is transferred to the ATL buffer or ITL buffer. The microprocessor detects the buffer status through the interrupt routines. When the HcBufferStatus register (2CH - read only) indicates that the buffer is empty, then the microprocessor writes data into the buffer. When the HcBufferStatus register indicates that the buffer is full, the data is ready on the buffer,and the microprocessor needs to read data from the buffer.

During every 1 ms, there might be many events to generate interrupt requests to the microprocessor for data transfer or status retrieval. However, each of the interrupt types deﬁned in this speciﬁcation can be enabled or disabled by setting the HcµPInterruptEnable register bits accordingly.

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The data transfer can be done via the PIO mode or the DMA mode. The data transfer rate can go up to 15 Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes are supported. Multi-cycle burst modes of 1, 4, or 8 cycles per burst is supported for ISP1161A.

9.4.2 Data organization

PTD data is used for every data transfer between a microprocessor and the USB bus, and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the payload data is placed just after the PTD, after which the next PTD is placed. For an IN transfer,RAMspace is reservedforreceiving a number of bytes that is equal to the total bytes of the transfer. After this, the next PTD and its payload data are placed (see Figure 27).

Remark: The PTD is deﬁned for both ATL and ITL type data transfers. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1161A takes care of the Ping-Pong action for the ITL buffer RAM access.

ISP1161A

Full-speed USB single-chip host and device controller

RAM buffer

top

PTD of OUT transfer

000H

payload data of OUT transfer

PTD of IN transfer

empty space for IN total data

PTD of OUT transfer

payload data of OUT transfer

bottom

Fig 27. Buffer RAM data organization.

7FFH

MGT952

The PTD data (PTD header and its payload data) is a structure of DWORD (doubleword or 4-byte) alignment. This means that the memory address is organized in blocks of 4 bytes. Therefore, the ﬁrst byte of every PTD and the ﬁrst byte of every payload data are located at an address which is a multiple of 4. Figure 28 illustrates an example in which the ﬁrst payload data is 14 bytes long, meaning that the last byte of the payload data is at the location 15H. The next addresses (16H and 17H) are not multiples of 4. Therefore, the ﬁrst byte of the next PTD will be located at the next multiple-of-four address, 18H.

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Full-speed USB single-chip host and device controller

RAM buffer

PTD

(8 bytes)

payload data

(14 bytes)

PTD

(8 bytes)

payload data

00Htop

08H

15H

18H

20H

MGT953

Fig 28. PTD data with DWORD alignment in buffer RAM.

9.4.3 Operation and C program example

Figure 29 shows the block diagram for internal FIFO buffer RAM operations in PIO

mode. The ISP1161A provides one register as the access port for each buffer RAM. Forthe ITL buffer RAM, the access port is the ITLBufferPort register (40H - read, C0H

- write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H read, C1H - write). The buffer RAM is an array of bytes (8 bits) while the access port is a 16-bit register. Therefore, each read/write operation on the port accesses two consecutive memory locations, incrementing the pointer of the internal bufferRAM by two. The lower byte of the access port register corresponds to the data byte at the even location of the buffer RAM, and the upper byte corresponds to the next data byte at the odd location of the buffer RAM. Regardless of the number of data bytes to be transferred, the command code must be issued merely once, and it will be followed by a number of accesses of the data port (see Section 8.4).

When the pointer of the buffer RAM reaches the value of the HcTransferCounter register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the HcµPinterrupt register and update the HcBufferStatus register, to indicate that the whole data transfer has been completed.

For ITL buffer RAM, every Start Of Frame (SOF) signal (1 ms) will cause toggling between ITL0 and ITL1, but this depends on the buffer status. If both ITL0BufferFull and ITL1BufferFull of the HcBufferStatus register are already logic 1, meaning that both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the microprocessor will always have access to ITL1.

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Host bus I/F

command port

data port

22H/A2H 24H/A4H

2CH 40H/C0H 41H/C1H

Full-speed USB single-chip host and device controller

Control registers

TransferCounter

µPInterrupt

BufferStatus

ITLBufferPort

ATLBufferPort

(16-bit width)

Commands

Command register

toggle

EOT

internal EOT

ISP1161A

SOF

BufferStatus

000H 001H

3FFH

ITL0 buffer RAM

(8-bit width)

000H 001H

3FFH

Fig 29. PIO access to internal FIFO buffer RAM.

Following is an example of a C program that shows how to write data into the ATL buffer RAM. The total number of data bytes to be transferred is 80 (decimal) which will be set into the HcTransferCounterregister as 50H. The data consists of four types of PTD data:

1. The ﬁrst PTD header (IN) is 8 bytes, followed by 16 bytes of space reserved for its payload data;

2. The second PTD header (IN) is also 8 bytes, followed by 8 bytes of space reserved for its payload data;

3. The third PTD header (OUT) is 8 bytes, followed by 16 bytes of payload data with values beginning from 0H to FH incrementing by 1;

4. The fourth PTD header (OUT) is also 8 bytes, followed by 8 bytes of payload data with values beginning from 0H to EH incrementing by 2.

ITL1 buffer RAM

(8-bit width)

000H 001H

7FFH

ATL buffer RAM

(8-bit width)

Pointer

automatically

increments by 2

MGT951

In all PTDs, we have assigned device address as 5 and endpoint as 1. ActualBytes is always zero (0). TotalBytes equals the number of payload data bytes transferred, however, note that for bulk and control transfers, TotalBytes can be greater than MaxPacketSize.

Table 6 shows the results after running this program.

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However,if communication with a peripheral USB device is desired, the device should be connected to the downstream port and pass enumeration.

// The example program for writing ATL buffer RAM #include <conio.h> #include <stdio.h> #include <dos.h>

// Define register commands #define wHcTransferCounter 0x22 #define wHcuPInterrupt 0x24 #define wHcATLBufferLength 0x2b #define wHcBufferStatus 0x2c

// Define I/O Port Address for HC #define HcDataPort 0x290 #define HcCmdPort 0x292

// Declare external functions to be used unsigned int HcRegRead(unsigned int wIndex); void HcRegWrite(unsigned int wIndex,unsigned int wValue);

ISP1161A

Full-speed USB single-chip host and device controller

void main(void) { unsigned int i; unsigned int wCount,wData;

// Prepare PTD data to be written into HC ATL buffer RAM: unsigned int PTDData[0x28]= {

0x0800,0x1010,0x0810,0x0005, // PTD header for IN token #1

// Reserved space for payload data of IN token #1 0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000,

0x0800,0x1008,0x0808,0x0005, // PTD header for IN token #2

// Reserved space for payload data of IN token #2 0x0000,0x0000,0x0000,0x0000,

0x0800,0x1010,0x0410,0x0005, // PTD header for OUT token #1

0x0100,0x0302,0x0504,0x0706, // Payload data for OUT token #1 0x0908,0x0b0a,0x0d0c,0x0f0e,

0x0800,0x1808,0x0408,0x0005, // PTD header for OUT token #2

0x0200,0x0604,0x0a08,0x0e0c // Payload data for OUT token #2 }; HcRegWrite(wHcuPInterrupt,0x04); // Clear EOT interrupt bit // HcRegWrite(wHcITLBufferLength,0x0); HcRegWrite(wHcATLBufferLength,0x1000); // RAM full use for ATL // Set the number of bytes to be transferred HcRegWrite(wHcTransferCounter,0x50);

wCount = 0x28; // Get word count outport (HcCmdPort,0x00c1); // Command for ATL buffer write

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// Write 80 (0x50) bytes of data into ATL buffer RAM for (i=0;i<wCount;i++) { outport(HcDataPort,PTDData[i]); };

// Check EOT interrupt bit wData = HcRegRead(wHcuPInterrupt); printf("\n HC Interrupt Status = %xH.\n",wData);

// Check Buffer status register wData = HcRegRead(wHcBufferStatus); printf("\n HC Buffer Status = %xH.\n",wData); }

// // Read HC 16-bit registers // unsigned int HcRegRead(unsigned int wIndex) { unsigned int wValue;

ISP1161A

Full-speed USB single-chip host and device controller

outport(HcCmdPort,wIndex & 0x7f); wValue = inport(HcDataPort);

return(wValue);

} // // Write HC 16-bit registers // void HcRegWrite(unsigned int wIndex,unsigned int wValue) { outport(HcCmdPort,wIndex | 0x80); outport(HcDataPort,wValue); }

Table 6: Run results of the C program example

Observed items HC notinitializedandnot in

USBOperational state

HcµPinterrupt register

Bit 1 (ATLInt) 0 1 microprocessor must read ATL Bit 2 (AllEOTInterrupt) 1 1 transfer completed

HcBufferStatus register

Bit 2 (ATLBufferFull) 1 1 transfer completed Bit 5 (ATLBufferDone) 0 1 PTD data processed by HC USB Trafﬁc on USB Bus No Yes OUT packets can be seen

HC initialized and in USBOperational state

Comments

9.5 HC operational model

Upon power-up, the HCD initializes all operational registers (32-bit). The FSLargestDataPacket ﬁeld (bits 30 to 16) of the HcFmInterval register (0DH - read, 8DH - write) and the HcLSThreshold register (11H - read, 91H - write) determine the

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end of the frame for full-speed and low-speed packets. By programming these ﬁelds, the effectiveUSB bus usage can be changed. Furthermore,the size of the ITL buffers (HcITLBufferLength, 2AH - read, AAH - write) is programmed.

In the case when a USB frame contains both ISO and AT packets, two interrupts will be generated per frame.

One interrupt is issued concurrently with the SOF.This interrupt (the ITLint bit is set in the HcµPInterrupt register) triggers reading and writing of the ITL buffer by the microprocessor, after which the interrupt is cleared by the microprocessor.

Next the programmable ATL Interrupt (the ATLint bit is set in the HcµPInterrupt register) is issued, which triggers reading and writing of the ATL buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. If the microprocessor cannot handle the ISO interrupt before the next ISO interrupt, disrupted ISO trafﬁc can result.

To be able to send more than one packet to the same Control or Bulk endpoint in the same frame, an Active bit and a TotalBytes ﬁeld are introduced (see Table 5). The Active bit is cleared only if all data of the Philips Transfer Descriptor (PTD) has been transferredor if a transaction at that endpoint contained a fatal error. If all PTDs of the ATL are serviced, and the frame is not over yet, the HC starts looking for a PTD with the Active bit still set. If such a PTD is found and there is still enough time in this frame, another transaction is started on the USB bus for this endpoint.

ISP1161A

Full-speed USB single-chip host and device controller

For ISO processing, the HCD also has to take care of the HCBufferStatus register (2CH, read only) for the ITL buffer RAM operations. After the HCD writes ISO data into ITL buffer RAM, the ITL0BufferFull or ITL1BufferFull bit (depends if it is ITL0 or ITL1) will be set to logic 1.

After the HC processes the ISO data in the ITL buffer RAM, the corresponding ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.The HCD can clear the buffer status bits by a read of the ITL buffer RAM. This must be done within the 1 ms frame from which the ITL0BufferDone or ITL1BufferDone was set.

For example, the HCD writes ISO_A data into the ITL0 buffer in the ﬁrst frame. This will cause the HCBufferStatus register to show that the ITL0 buffer is full by setting the ITL0BufferFull bit to logic 1. At this stage the HCD cannot write ISO data into the ITL0 buffer RAM again.

In the second frame, the HC will process the ISO-A data in the ITL0 buffer. At the same time, the HCD can write ISO-B data into ITL1 buffer. When the next SOF comes (the beginning of the third frame), both the ITL1BufferFull and ITL0BufferDone are automatically set to logic 1.

In the third frame the HCD has to read at least two bytes (one word) of the ITL0 buffer to clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not cleared, when the next SOF comes (the beginning of the fourth frame) the ITL0BufferDone and ITL0BufferFull bits will be cleared automatically. This also applies to the ITL1 buffer because the ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a power-on reset or software reset will have to be applied.

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9.5.1 Time domain behavior

In example 1 (Figure 30), the microprocessor is fast enough to read back and download a scenario before the next interrupt. Note that on the ISO interrupt of frame N:

• The ISO packet for frame N + 1 will be written

• The AT packet for frame N + 1 will be written.

SOF

(frame N) (frame N + 1) (frame N + 2) (frame N + 3)

traffic

on USB

interrupt

ISP1161A

Full-speed USB single-chip host and device controller

ISO

interrupt

read ISO_A(N − 1) write ISO_A(N + 1)

Fig 30. HC time domain behavior: example 1.

In example 2 (Figure 31), the microprocessor is still busy transferring the AT data when the ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no AT trafﬁc in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The AT part is simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer mechanism is back to normal operation. This simple mechanism ensures, among other things, that Control transfers are not dropped systematically from the USB in case of an overloaded microprocessor.

(frame N) (frame N + 1) (frame N + 2) (frame N + 3)

MGT954

read AT(N) write AT(N + 1)

MGT955

Fig 31. HC time domain behavior: example 2.

In example 3 (Figure 32), the ISO part is still being written while the Start of Frame (SOF) of the next frame has occurred. This will result in undeﬁned behavior for the ISO data on the USB bus in frame N + 1 (depending on if the exact timing data is corrupted or not). The HC should not raise an AT interrupt in frame N + 1.

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(frame N) (frame N + 1) (frame N + 2) (frame N + 3)

Fig 32. HC time domain behavior: example 3.

9.5.2 Control transaction limitations

The different phases of a Control transfer (SETUP,Data and Status) should never be put in the same ATL.

9.6 Microprocessor loading

The maximum amount of data that can be transferred for an endpoint during one frame is 1023 bytes. The number of USB packets that are needed for this batch of data depends on the maximum packet size that is speciﬁed.

ISP1161A

Full-speed USB single-chip host and device controller

MGT956

The HCD has to schedule the transactions in a frame. On the other hand, the HCD must have the ability to handle the interrupts coming from the HC every 1 ms. It must also be able to do the scheduling for the next frame, reading the frame information from and writing the next frame information to the bufferRAM in the time between the end of the current frame and the start of the next frame.

9.7 Internal pull-down resistors for downstream ports

There are four internal 15 kΩ pull-down resistors built into the ISP1161A for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15K resistorsel) of the HcHardwareConﬁguration register (20H - read, A0H - write). When bit 12 is logic 0, external 15 kΩ pull-down resistors are used. If bit 12 is set to logic 1, the internal 15 kΩ pull-down resistors are used. See Figure 33.

This feature is a cost-saving option. However, the power-on reset default value of bit 12 is logic 0. If using the internal resistors, the HCD must set this bit status after every reset, because a reset action (hardware or software) will clear this bit.

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ISP1161A

Full-speed USB single-chip host and device controller

HcHardware

Configuration

ISP1161A

bit 12

internal

15 kΩ

(2×)

D− D+

004aaa088

22 Ω

external

15 kΩ

(2×)

BUS

connector

47 pF

(2×)

USB

Using either internal or external 15 kΩ resistors.

Fig 33. Use of 15 kΩ pull-down resistors on downstream ports.

9.8 OC detection and power switching control

A downstream port provides 5 V power supply to V hardware functions to monitor the downstream ports loading conditions and control their power switching. These hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit. H_PSW1 and H_PSW2 are power switching control output pins (active LOW, open drain) for downstream port 1 and 2, respectively. H_OC1 and H_OC2 are overcurrent detection input pins for downstream ports 1 and 2, respectively.

. The ISP1161A has built-in

BUS

Figure 34 shows the ISP1161A downstream port power management scheme

(‘n’ represents the downstream port numbers, n=1or2).

regulator

OC select

Reg

PSW

C/L

HC CORE

HcHardware

Configuration

bit 10

004aaa089

(+5 V or +3.3 V)

OC detect

H_OCn

H_PSWn

≥

ISP1161A

‘n’ represents the downstream port number (n=1or2)

Fig 34. Downstream port power management scheme.

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9.8.1 Using an internal OC detection circuit

The internal OC detection circuit can be used only when VCC(pin 56) is connected to a 5 V power supply. The HCD must set AnalogOCEnable, bit 10 of the HcHardwareConﬁguration register, to logic 1.

An application using the internal OC detection circuit and internal 15 kΩ pull-down resistors is shown in Figure 35. In this example, the HCD must set both AnalogOCEnable and DownstreamPort15KresistorSel to logic 1. They are bit 10 and bit 12 of the HcHardwareConﬁguration register, respectively.

When H_OCn detects an overcurrent status on a downstream port, H_PSWn will output HIGH, logic 1 to turn off the 5 V power supply to the downstream port V When there is no such condition, H_PSWn will output LOW,logic 0 to turn on the 5 V power supply to the downstream port V

In general applications, a P-channel MOSFET can be used as the power switch for V

BUS

the drain, and H_PSWn to the gate. Call the voltage drop across the drain and source the overcurrent detection voltage (VOC). For the internal overcurrent detection circuit, a voltage comparator has been incorporated with a nominal voltage threshold (∆V of 75 mV. When VOC exceeds V off the P-channel MOSFET. If the P-channel MOSFET has a R overcurrent threshold will be 500 mA. The selection of a P-channel MOSFET with a different R

ISP1161A

Full-speed USB single-chip host and device controller

BUS

. Connect the 5 V power supply to the source of the P-channel MOSFET, V

, H_PSWn will output a HIGH level, logic 1 to turn

trip

of 150 mΩ, the

DSon

will result in a different overcurrent threshold.

DSon

BUS

trip

)

P-Ch

MOSFET

5 V

∆V = +5 V − V

BUS

‘n’ represents the downstream port number (n=1or2)

BUS

USB

downstream

port

connector

47 pF

(2×)

Fig 35. Using internal OC detection circuit.

22 Ω

H_OCn

H_PSWn

H_DMn

H_DPn

regulator

OC detect

≥

15 kΩ

(2×)

bit 12

OC select

Reg

PSW

C/L

ATX

HcHardware

Configuration

HC CORE

HcHardware

Configuration

bit 10

SIE

ISP1161A

004aaa090

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9.8.2 Using an external OC detection circuit

When VCC (pin 56) is connected to a 3.3 V instead of the 5 V power supply, the internal OC detection circuit cannot be used. An external OC detection circuit must be used instead. Regardless of the VCC value, an external OC detection circuit can always be used. To use an external OC detection circuit, AnalogOCEnable, bit 10 of the HcHardwareConﬁguration register, must be logic 0. By default after reset, this bit is already logic 0; therefore, the HCD does not need to clear this bit.

Figure 36 shows how to use an external OC detection circuit.

BUS

downstream

connector

external

OC detect

VoV

OC EN

USB

port

ISP1161A

Full-speed USB single-chip host and device controller

3.3 V or +5 V

5 V

22 Ω

H_OCn

H_PSWn

H_DMn

regulator

OC detect

≥

OC select

Reg

PSW

C/L

HC CORE

HcHardware

Configuration

bit 10

22 Ω

47 pF

(2×)

‘n’ represents the downstream port number (n=1or2)

Fig 36. Using an external OC detection circuit.

9.9 Suspend and wake-up

9.9.1 HC suspended state

The HC can be put into suspended state by setting the HcControl register (01H read, 81H - write). See Figure 23 for the HC’s ﬂow of USB state changes.

H_DPn

bit 12

15 kΩ

(2×)

ATX

HcHardware

Configuration

SIE

ISP1161A

004aaa091

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ISP1161A

Full-speed USB single-chip host and device controller

XOSC

VOLTAGE

REGULATOR

XOSC_6MHz

(to DC PLL)

DC_EnableClock

PLL_Lock

HC PLL

PLL_ClkOut

HC_EnableClock

Fig 37. ISP1161A suspend and resume clock scheme.

In suspended state, the device will consume considerably less power by turning off the internal 48 MHz clock, PLL and crystal, and setting the internal regulator to power-down mode. The ISP1161A suspend and resume clock scheme is shown in

Figure 37.

Remark: The ISP1161A can only be put into a fully suspended state only after both the HC and the DC go into suspend state. At this point, the crystal can be turned off and the internal regulator can be put into power-down mode.

HC_ClkOk

HC_RawClk48M

HcHardware Configuration

bit 11 (SuspendClkNotStop)

H_Wakeup (pin)

DIGITAL

CLOCK

SWITCH

HC_Clk48MOut

HC_NeedClock

CS (pin)

CORE

MGT958

Pin H_SUSPEND is the sensing output pin for HC’s suspended state. When the HC goes into USBSuspend state, this pin will output a HIGH level (logic 1). This pin is cleared to LOW (logic 0) level only when the HC is put into a USBReset state or USBOperational state (refer to the HcControl register bits 7 to 6, 01H - read, 81H write). Bit 11, SuspendClkNotStop, of the HcHardwareConﬁguration register (20H read, A0H - write), deﬁnes if the HC internal clock is stopped or kept running when the HC goes into USBSuspend state. After the HC enters the USBSuspend state for

1.3 ms, the internal clock will be stopped if bit SuspendClkNotStop is logic 0.

9.9.2 HC wake-up from suspended state

There are three methods to wake up the HC from the USBSuspend state: hardware wake-up, software wake-up, and USB bus resume.

They are described as follows:

• Wake-up by pin H_WAKEUP

Pins H_SUSPEND and H_WAKEUP provide a method of remote wake-up control for the HC without the need to access the HC internal registers. H_WAKEUP is an external wake-up control input pin for the HC. After the HC goes into USBSuspend state, it can be woken up by sending a HIGH level pulse to pin H_WAKEUP. This will turn on the HC’s internal clock, and set bit 6, ClkReady, of the HcµPInterrupt register (24H - read, A4H - write).

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• Wake-up by pin CS (software wake-up)

• Wake-up by USB devices

No matter which method is used to wake up the HC from USBSuspend state, the corresponding interrupt bits must be enabled before the HC goes into USBSuspend state so that the microprocessor can receive the correct interrupt request to wake up the HC.

ISP1161A

Full-speed USB single-chip host and device controller

Under the USBSuspend state, once pin H_WAKEUP goes HIGH, after 160 µs, the internal clock will be up. If pin H_WAKEUP continues to be HIGH, then the internal clock will be kept running, and the microprocessor can set the HC into USBOperational state during this time.

If H_WAKEUP goes LOW for more than 1.14 ms, the internal clock stops, and the HC goes back into USBSuspend state.

During the USBSuspend state, an external microprocessor issues a chip select signal through pin CS. This method of access to ISP1161A internal registers is a software wake-up.

For a USB bus resume, a USB device attached to the root hub port issues a resume signal to the HC through the USB bus, switching the HC from USBSuspend state to USBResume state. This will also set the ResumeDetected bit of the HcInterruptStatus register (03H - read, 83H - write).

10. HC registers

The HC contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter register sets, and Root Hub register sets are grouped under the category of HC Operational registers (32 bits). These operational registers are made compatible to OpenHCI (Host Controller Interface) Operational registers. This allows the OpenHCI HCD to be easily ported to ISP1161A.

Reserved bits may be deﬁned in future releases of this speciﬁcation. To ensure interoperability, the HCD must not assume that a reserved ﬁeld contains logic 0. Furthermore, the HCD must always preserve the values of the reserved ﬁeld. When a R/W register is modiﬁed, the HCD must ﬁrst read the register, modify the bits desired, and then write the register with the reserved bits still containing the original value. Alternatively, the HCD can maintain an in-memory copy of previously written values that can be modiﬁed and then written to the HC register. When a ‘write to set’ or ‘clear the register’ is performed, bits written to reserved ﬁelds must be logic 0.

As shown in Table 7, the addresses (the commands for accessing registers) of these 32-bit Operational registers are similar the offsets deﬁned in the OHCI speciﬁcation with the addresses being equal to offset divided by 4.

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ISP1161A

Full-speed USB single-chip host and device controller

Table 7: HC registers summary

Address (Hex) Register Width Reference Functionality

read write

00 - HcRevision 32 Section 10.1.1 on page 44 HC Control and Status registers 01 81 HcControl 32 Section 10.1.2 on page 45 02 82 HcCommandStatus 32 Section 10.1.3 on page 46 03 83 HcInterruptStatus 32 Section 10.1.4 on page 48 04 84 HcInterruptEnable 32 Section 10.1.5 on page 49 05 85 HcInterruptDisable 32 Section 10.1.6 on page 50 0D 8D HcFmInterval 32 Section 10.2.1 on page 52 HC Frame Counter registers 0E - HcFmRemaining 32 Section 10.2.2 on page 53 0F - HcFmNumber 32 Section 10.2.3 on page 53 11 91 HcLSThreshold 32 Section 10.2.4 on page 54 12 92 HcRhDescriptorA 32 Section 10.3.1 on page 56 HC Root Hub registers 13 93 HcRhDescriptorB 32 Section 10.3.2 on page 57 14 94 HcRhStatus 32 Section 10.3.3 on page 59 15 95 HcRhPortStatus[1] 32 Section 10.3.4 on page 61 16 96 HcRhPortStatus[2] 32 Section 10.3.4 on page 61 20 A0 HcHardwareConﬁguration 16 Section 10.4.1 on page 65 HC DMA and Interrupt Control 21 A1 HcDMAConﬁguration 16 Section 10.4.2 on page 66 22 A2 HcTransferCounter 16 Section 10.4.3 on page 67 24 A4 HcµPInterrupt 16 Section 10.4.4 on page 68 25 A5 HcµPInterruptEnable 16 Section 10.4.5 on page 69 27 - HcChipID 16 Section 10.5.1 on page 70 HC Miscellaneous registers 28 A8 HcScratch 16 Section 10.5.2 on page 71

- A9 HcSoftwareReset 16 Section 10.5.3 on page 71 2A AA HcITLBufferLength 16 Section 10.6.1 on page 72 HC Buffer RAM Control registers 2B AB HcATLBufferLength 16 Section 10.6.2 on page 72 2C - HcBufferStatus 16 Section 10.6.3 on page 73 2D - HcReadBackITL0Length 16 Section 10.6.4 on page 74 2E - HcReadBackITL1Length 16 Section 10.6.5 on page 74 40 C0 HcITLBufferPort 16 Section 10.6.6 on page 75 41 C1 HcATLBufferPort 16 Section 10.6.7 on page 75

registers

10.1 HC control and status registers

10.1.1 HcRevision register (R: 00H)

Code (Hex): 00 — read only

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ISP1161A

Full-speed USB single-chip host and device controller

Table 8: HcRevision register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol REV[7:0] Reset 00010000 Access RRRRRRRR

Table 9: HcRevision register: bit description

Bit Symbol Description

31 to 8 − Reserved 7 to 0 REV[7:0] Revision: This read-only ﬁeld contains the BCD representation of

the version of the HCI speciﬁcation that is implemented by this HC. For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this speciﬁcation will have a value of 10H.

10.1.2 HcControl register (R/W: 01H/81H)

The HcControl register deﬁnes the operating modes for the HC. RemoteWakeupEnable (RWE) is modiﬁed only by the HCD.

Code (Hex): 01 — read Code (Hex): 81 — write

Table 10: HcControl register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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ISP1161A

Full-speed USB single-chip host and device controller

Bit 15 14 13 12 11 10 9 8 Symbol reserved RWE RWC reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol HCFS[1:0] reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 11: HcControl register: bit description

Bit Symbol Description

31 to 11 - reserved 10 RWE RemoteWakeupEnable: This bit is used by the HCD to enable or

disable the remote wake-up feature upon the detection of upstream resume signaling. When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote wake-up is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt.

9RWCRemoteWakeupConnected: This bit indicates whether the HC

supports remote wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of system ﬁrmware to set this bit during POST. The HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wake-up signaling of the host system is host-bus-speciﬁc,

and is not described in this speciﬁcation. 8 - reserved 7 to 6 HCFS HostControllerFunctionalState for USB:

00B — USBReset

01B — USBResume

10B — USBOperational

11B — USBSuspend

A transition to USBOperational from another state causes

start-of-frame (SOF) generation to begin 1 ms later. The HCD

determines whether the HC has begun sending SOFs by reading

the StartofFrame ﬁeld of HcInterruptStatus.

This ﬁeld can be changed by the HC only when in the

USBSuspend state. The HC can move from the USBSuspend

state to the USBResumestateafterdetectingthe resume signaling

from a downstream port.

The HC enters USBReset after a software reset and a hardware

reset. The latter also resets the Root Hub and asserts subsequent

reset signaling to downstream ports. 5 to 0 - reserved

10.1.3 HcCommandStatus register (R/W: 02H/82H)

The HcCommandStatus register is used by the HC to receive commands issued by the HCD, and it also reﬂects the HC’s current status. To the HCD, it appears to be a ‘write to set’ register. The HC must ensure that bits written as logic 1 become set in

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the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the HC without concern for corrupting previously issued commands. The HCD has normal read access to all bits.

The SchedulingOverrunCount ﬁeld indicates the number of frames with which the HC has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the HC increments the counter and sets the SchedulingOverrun ﬁeld in the HcInterruptStatus register.

Code (Hex): 02 — read Code (Hex): 82 — write

Table 12: HcCommandStatus register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 23 22 21 20 19 18 17 16 Symbol reserved SOC[1:0] Reset 00000000 Access RRRRRRRR Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved HCR Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Table 13: HcCommandStatus register: bit description

Bit Symbol Description

31 to 18 - reserved 17 to 16 SOC[1:0] SchedulingOverrunCount: The ﬁeld is incremented on each

15 to 1 - reserved 0 HCR HostControllerReset: This bit is set by the HCD to initiate a

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Full-speed USB single-chip host and device controller

scheduling overrun error. It is initialized to 00B and wraps around

at 11B. It will be incremented when a scheduling overrun is

detected even if SchedulingOverrun in HcInterruptStatus has

already been set. This is used by HCD to monitor any persistent

scheduling problems.

software reset of the HC. Regardless of the functional state of HC,

it movestothe USBSuspend state in which most of the operational

registers are reset, except those stated otherwise, and no Host

bus accesses are allowed. This bit is cleared by HC upon the

completion of the reset operation. The reset operation must be

completed within 10 µs. This bit, when set, does not cause a reset

to the Root Hub and no subsequent reset signaling will be

asserted to its downstream ports.

10.1.4 HcInterruptStatus register (R/W: 03H/83H)

This register provides the status of the events that cause hardware interrupts. When an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register (see Section 10.1.5) and the MasterInterruptEnable bit is set. The HCD can clear individual bits in this register by writing logic 1 to the bit positions to be cleared, but cannot set any of these bits. Conversely, the HC can set bits in this register, but cannot clear the bits.

Code (Hex): 03 — read Code (Hex): 83 — write

Table 14: HcInteruptStatus register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Bit 7 6 5 4 3 2 1 0 Symbol reserved RHSC FNO UE RD SF reserved SO Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 15: HcInterruptStatus register: bit description

Bit Symbol Description

31 to 7 reserved 6 RHSC RootHubStatusChange: This bit is set when the content of

HcRhStatus or the content of any of HcRhPortStatus[1:2] has

changed. 5 FNO FrameNumberOverﬂow: This bit is set when the MSB of

HcFmNumber (bit 15) changes value. 4UEUnrecoverableError: This bit is set when the HC detects a

system error not related to USB. The HC does not proceed with

any processing nor signaling before the system error has been

corrected. The HCD clears this bit after the HC has been reset.

OHCI: Always set to logic 0. 3RDResumeDetected: This bit is set when the HC detects that a

device on the USB is asserting resume signaling from a state of no

resume signaling. This bit is not set when HCD enters the

USBResume state. 2SFStartofFrame: At the start of each frame, this bit is set by the HC

and an SOF is generated. 1 - reserved 0SOSchedulingOverrun: This bit is set when the USB schedules for

current frame overruns. A scheduling overrun will also cause the

SchedulingOverrunCount of HcCommandStatus to be

incremented.

10.1.5 HcInterruptEnable register (R/W: 04H/84H)

Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. A hardware interrupt is requested on the host bus when three conditions occur:

• A bit is set in the HcInterruptStatus register

• The corresponding bit in the HcInterruptEnable register is set

• The MasterInterruptEnable bit is set.

Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned.

Code (Hex): 04 — read Code (Hex): 84 — write

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Table 16: HcInterruptEnable register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol MIE reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved RHSC FNO UE RD SF reserved SO Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 17: HcInterruptEnable register: bit description

Bit Symbol Description

31 MIE MasterInterruptEnable by the HCD: Logic 0 is ignored by the HC.

Logic 1 enables interrupt generation by events speciﬁed in other

bits of this register. 30 to 7 - reserved 6 RHSC 0 — ignore

1 — enable interrupt generation due to Root Hub Status Change 5 FNO 0 — ignore

1 — enable interrupt generation due to Frame Number Overﬂow 4UE0 — ignore

1 — enable interrupt generation due to Unrecoverable Error 3RD0 — ignore

1 — enable interrupt generation due to Resume Detect 2SF0 — ignore

1 — enable interrupt generation due to Start of Frame 1 - reserved 0SO0 — ignore

1 — enable interrupt generation due to Scheduling Overrun

10.1.6 HcInterruptDisable register (R/W: 05H/85H)

Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas

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writing logic 0 to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a read, the current value of the HcInterruptEnable register is returned.

Code (Hex): 05 — read Code (Hex): 85 — write

Table 18: HcInterruptDisable register: bit allocation

Table 19: HcInterruptDisable register: bit description

Bit Symbol Description

31 MIE Logic 0 is ignored by the HC. Logic 1 disables interrupt generation

due to events speciﬁed in other bits of this register. This bit is set

after a hardware or software reset. 30 to 7 - reserved 6 RHSC 0 — ignore

1 — disable interrupt generation due to Root Hub Status Change 5 FNO 0 — ignore

1 — disable interrupt generation due to Frame Number Overﬂow 4UE0 — ignore

1 — disable interrupt generation due to Unrecoverable Error 3RD0 — ignore

1 — disable interrupt generation due to Resume Detect 2SF0 — ignore

1 — disable interrupt generation due to Start of Frame 1 - reserved 0SO0 — ignore

1 — disable interrupt generation due to Scheduling Overrun

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10.2 HC frame counter registers

10.2.1 HcFmInterval register (R/W: 0DH/8DH)

The HcFmIntervalregister contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the full-speed maximum packet size that the HC may transmit or receive without causing a scheduling overrun. The HCD may carry out minor adjustments on the FrameIntervalby writing a new value at each SOF. This allows the HC to synchronize with an external clock source and to adjust any unknown clock offset.

Code (Hex): 0D — read Code (Hex): 8D — write

Table 20: HcFmInterval register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol FIT FSMPS[14:8] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol FSMPS[7:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol reserved FI[13:8] Reset 00101110 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol FI[7:0] Reset 11011111 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 21: HcFmInterval register: bit description

Bit Symbol Description

31 FIT FrameIntervalToggle: The HCD toggles this bit whenever it loads

a new value to FrameInterval. 30 to 16 FSMPS

[14:0]

15 to 14 - reserved 13 to 0 FI[13:0] FrameInterval: Speciﬁes the interval between two consecutive

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FSLargestDataPacket (FSMaximumPacketSize): Speciﬁes a

value which is loaded into the Largest Data Packet Counter at the

beginning of each frame. The counter value represents the largest

amount of data in bits which can be sent or received bythe HC in a

single transaction at any given time without causing a scheduling

overrun. The ﬁeld value is calculated by the HCD.

SOFs in bit times. The default value is 11999. The HCD must save

the current value of this ﬁeld before resetting the HC. Setting the

HostControllerReset of the HcCommandStatus register will cause

the HC to reset this ﬁeld to its default value. HCD may choose to

restore the saved value upon completing the Reset sequence.

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10.2.2 HcFmRemaining register (R: 0EH)

The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame.

Code (Hex): 0E — read

Table 22: HcFmRemaining register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol FRT reserved Reset 00000000 Access RRRRRRRR Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 15 14 13 12 11 10 9 8 Symbol reserved FR[13:8] Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol FR[7:0] Reset 00000000 Access RRRRRRRR

Table 23: HcFmRemaining register: bit description

Bit Symbol Description

31 FRT FrameRemainingToggle: This bit is loaded from the

FrameIntervalToggle ﬁeld of the HcFmInterval register whenever

FrameRemaining reaches 0. This bit is used by the HCD for

synchronization between FrameInterval and FrameRemaining. 30 to 14 - reserved 13 to 0 FR[13:0] FrameRemaining: This counter is decremented at each bit time.

When it reaches zero, it is reset by loading the FrameIntervalvalue

speciﬁed in the HcFmInterval register at the nextbit time boundary.

When entering the USBOperational state, the HC reloads it with

the content of the FrameInterval part of the HcFmInterval register

and uses the updated value from the next SOF.

10.2.3 HcFmNumber register (R: 0FH)

The HcFmNumber register is a 16-bit counter. It provides a timing reference for events happening in the HC and the HCD. The HCD may use the 16-bit value speciﬁed in this register and generate a 32-bit frame number without requiring frequent access to the register.

Code (Hex): 0F — read

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Table 24: HCFmNumber register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 15 14 13 12 11 10 9 8 Symbol FN[15:8] Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol FN[7:0] Reset 00000000 Access RRRRRRRR

Table 25: HcFmNumber register: bit description

Bit Symbol Description

31 to 16 − reserved 15 to 0 FN[15:0] FrameNumber: This ﬁeld is incremented when HcFmRemaining

is reloaded. It rolls over to 0000H after FFFFH. When the

USBOperational state is entered, this ﬁeld will be incremented

automatically. HC will set the StartofFrame bit in the

HcInterruptStatus register.

10.2.4 HcLSThreshold register (R/W: 11H/91H)

The HcLSThreshold register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the HC nor the HCD is allowed to change this value.

Code (Hex): 11 — read Code (Hex): 91 — write

Table 26: HcLSThreshold register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Bit 15 14 13 12 11 10 9 8 Symbol reserved LST[10:8] Reset 00000110 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol LST[7:0] Reset 00101000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 27: HcLSThreshold register: bit description

Bit Symbol Description

31 to 11 − reserved 10 to 0 LST[10:0] LSThreshold: Contains a value that is compared to the

FrameRemaining ﬁeld before a low-speed transaction is initiated.

The transaction is started only if FrameRemaining ≥ this ﬁeld. The

value is calculated by the HCD, which considers transmission and

set-up overhead. Default value: 1576 (628H)

10.3 HC Root Hub registers

All registers included in this partition are dedicated to the USB Root Hub, which is an integral part of the HC although it is functionally a separate entity. The Host Controller Driver (HCD) emulates USBD accesses to the Root Hub via a register interface. The HCD maintains many USB-deﬁned hub features that are not required to be supported in hardware. For example, the Hub’s Device, Conﬁguration, Interface, Endpoint Descriptors, as well as some static ﬁelds of the Class Descriptor, are maintained only in the HCD. The HCD also maintains and decodes the Root Hub’s device address as well as other minor operations more suited for software than for hardware.

The Root Hub registers were developed to match the bit organization and operation of typical hubs found in the system.

Four 32-bit registers have been deﬁned:

• HcRhDescriptorA

• HcRhDescriptorB

• HcRhStatus

• HcRhPortStatus[1:NDP]

Each register is read and written as a DWORD. These registers are only written during initialization to correspond with the system implementation. The HcRhDescriptorA and HcRhDescriptorB registers are writeable regardless of the HC’s USB states. HcRhStatus and HcRhPortStatus are writeable during the USBOperational state only.

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10.3.1 HcRhDescriptorA register (R/W: 12H/92H)

The HcRhDescriptorA register is the ﬁrst register of two describing the characteristics of the Root Hub. Reset values are Implementation-Speciﬁc (IS). The descriptorlength (11), descriptor type and hub controller current (0) ﬁelds of the hub Class Descriptor are emulated by the HCD. All other ﬁelds are located in the registers HcRhDescriptorA and HcRhDescriptorB.

Remark: IS denotes an implementation-speciﬁc reset value for that ﬁeld. Code (Hex): 12 — read

Code (Hex): 92 — write

Table 28: HcRhDescriptorA register: bit description

Bit 31 30 29 28 27 26 25 24 Symbol POTPGT[7:0] Reset IS IS IS IS IS IS IS IS Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol reserved NOCP OCPM DT NPS PSM Reset 0 0 0 IS IS 0 IS IS Access R R R R/W R/W R R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved NDP[1:0] Reset 000000ISIS Access RRRRRRRR

Table 29: HcRhDescriptorA register: bit description

Bit Symbol Description

31 to 24 POTPGT

[7:0]

23 to 13 - reserved

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PowerOnToPowerGoodTime: This byte speciﬁes the duration

HCD has to wait before accessing a powered-on port of the Root

Hub. The unit of time is 2 ms. The duration is calculated as

POTPGT × 2ms.

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Table 29: HcRhDescriptorA register: bit description

Bit Symbol Description

12 NOCP NoOverCurrentProtection: This bit describes how the

overcurrent status for the Root Hub ports are reported. When this

bit is cleared, the OverCurrentProtectionMode ﬁeld speciﬁes

global or per-port reporting.

0 — overcurrent status is reported collectively for all downstream

ports

1 — no overcurrent reporting supported 11 OCPM OverCurrentProtectionMode: This bit describes how the

overcurrent status for the Root Hub ports is reported. At reset, this

ﬁeld reﬂects the same mode as PowerSwitchingMode.This ﬁeld is

valid only if the NoOverCurrentProtection ﬁeld is cleared.

0 — overcurrent status is reported collectively for all downstream

ports.

1 — overcurrent status is reported on a per-port basis. On

power-up, clear this bit and then set it to logic 1. 10 DT DeviceType: This bit speciﬁes that the Root Hub is not a

compound device—it is not permitted. This ﬁeld will always

read/write 0. 9 NPS NoPowerSwitching: These bits are used to specify whether

power switching is supported or ports are always powered. It is

implementation-speciﬁc. When this bit is cleared, the bit

PowerSwitchingMode speciﬁes global or per-port switching.

…continued

0 — ports are power switched

1 — ports are always powered on when the HC is powered on

8 PSM PowerSwitchingMode: This bit is used to specify how the power

switching of the Root Hub ports is controlled. It is

implementation-speciﬁc. This ﬁeld is valid only if the

NoPowerSwitching ﬁeld is cleared.

0 — all ports are powered at the same time

1 — each port is powered individually. This mode allows port

power to be controlled by either the global switch or per-port

switching. If the bit PortPowerControlMask is set, the port

responds to only port power commands (Set/ClearPortPower). If

the port mask is cleared, then the port is controlled only by the

global power switch (Set/ClearGlobalPower). 7 to 2 - reserved 1 to 0 NDP[1:0] NumberDownstreamPorts: These bits specify the number of

downstream ports supported by the Root Hub. The maximum

number of ports supported by ISP1161A is 2.

10.3.2 HcRhDescriptorB register (R/W: 13H/93H)

The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These ﬁelds are written during initialization to correspond with the system implementation. Reset values are implementation-speciﬁc (IS).

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Code (Hex): 13 — read Code (Hex): 93 — write

Table 30: HcRhDescriptorB register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset N/A N/A N/A N/A N/A N/A N/A N/A Access RRRRRRRR Bit 23 22 21 20 19 18 17 16 Symbol reserved PPCM[2:0] Reset N/A N/A N/A N/A N/A IS IS IS Access RRRRRR/WR/WR/W Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset N/A N/A N/A N/A N/A N/A N/A N/A Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol reserved DR[2:0] Reset N/A N/A N/A N/A N/A IS IS IS Access RRRRRR/WR/WR/W

Table 31: HcRhDescriptorB register: bit description

Bit Symbol Description

31 to 19 - reserved 18 to 16 PPCM[2:0] PortPowerControlMask: Each bit indicates whether a port is

affected by a global power control command when

PowerSwitchingMode is set. When set, the port’s power state is

only affected by per-port power control (Set/ClearPortPower).

When cleared, the port is controlled by the global power switch

(Set/ClearGlobalPower). If the device is conﬁgured to global

switching mode (PowerSwitchingMode = 0), this ﬁeld is not valid.

Bit 0 — reserved

Bit 1 — Ganged-power mask on Port #1

Bit 2 — Ganged-power mask on Port #2

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Table 31: HcRhDescriptorB register: bit description

Bit Symbol Description

15 to 3 - reserved 2 to 0 DR[2:0] DeviceRemovable: Each bit is dedicated to a port of the Root

Hub. When cleared, the attached device is removable. When set,

the attached device is not removable.

Bit 0 — reserved

Bit 1 — Device attached to Port #1

Bit 2 — Device attached to Port #2

…continued

10.3.3 HcRhStatus register (R/W: 14H/94H)

The HcRhStatus register is divided into two parts. The lower word of a DWORD represents the Hub Status ﬁeld and the upper word represents the Hub Status Change ﬁeld. Reserved bits should always be written as logic 0.

Code (Hex): 14 — read Code (Hex): 94 — write

Table 32: HcRhStatus register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol CRWE reserved Reset 00000000 Access WRRRRRRR Bit 23 22 21 20 19 18 17 16 Symbol reserved OCIC LPSC Reset 00000000 Access RRRRRRR/WR/W Bit 15 14 13 12 11 10 9 8 Symbol DRWE reserved Reset 00000000 Access R/WRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol reserved OCI LPS Reset 00000000 Access RRRRRRRR/W

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Table 33: HcRhStatus register: bit description

Bit Symbol Description

31 CRWE On write—ClearRemoteWakeupEnable: Writing logic 1 clears

30 to 18 - reserved 17 CCIC OverCurrentIndicatorChange: This bit is set byhardwarewhena

16 LPSC On read—LocalPowerStatusChange: The Root Hub does not

15 DRWE On read—DeviceRemoteWakeupEnable: This bit enables the bit

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DeviceRemoveWakeupEnable. Writing logic 0 has no effect.

change has occurred to the OCI ﬁeld of this register. The HCD

clears this bit by writing logic 1. Writing logic 0 has no effect.

support the local power status feature. Therefore,this bit is always

read as logic 0.

On write—SetGlobalPower: In global power mode

(PowerSwitchingMode=0), this bit is written to logic 1 to turn on

power to all ports (clear PortPowerStatus). In per-port power

mode, it sets PortPowerStatus only on ports whose bit

PortPowerControlMask is not set. Writing logic 0 has no effect.

ConnectStatusChange as a resume event, causing a state

transition USBSuspend to USBResume and setting the

ResumeDetected interrupt.

0 — ConnectStatusChange is not a remote wake-up event

1 — ConnectStatusChange is a remote wake-up event

On write—SetRemoteWakeupEnable: Writing logic 1 sets

DeviceRemoveWakeupEnable. Writing logic 0 has no effect. 14 to 2 - reserved 1 OCI OverCurrentIndicator: This bit reports overcurrent conditions

when global reporting is implemented. When set, an overcurrent

condition exists. When clear, all power operations are normal. If

per-port overcurrent protection is implemented this bit is always

logic 0. 0 LPS On read—LocalPowerStatus:The Root Hub does not support the

local power status feature. Therefore, this bit is always read as

logic 0.

On write—ClearGlobalPower: In global power mode

(PowerSwitchingMode = 0), this bit is written to logic 1 to turn off

power to all ports (clear PortPowerStatus). In per-port power

mode, it clears PortPowerStatus only on ports whose

PortPowerControlMask bit is not set. Writing logic 0 has no effect.

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10.3.4 HcRhPortStatus[1:2] register (R/W [1]:15H/95H, [2]: 16H/96H)

The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reﬂect the port status, whereas the upper word reﬂects the status change bits. Some status bits are implemented with special write behavior. If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. Reserved bits should always be written logic 0.

Code (Hex): [1] = 15, [2] = 16 — read Code (Hex): [1] = 95, [2] = 96 — write

Table 34: HcRhPortStatus[1:2] register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol reserved PRSC OCIC PSSC PESC CSC Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol reserved LSDA PPS Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved PRS POCI PSS PES CCS Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 35: HcRhPortStatus[1:2] register: bit description

Bit Symbol Description

31 to 21 - reserved 20 PRSC PortResetStatusChange: This bit is set at the end of the 10 ms

port reset signal. The HCD writes logic 1 to clear this bit. Writing

logic 0 has no effect.

0 — port reset is not complete

1 — port reset is complete

19 OCIC PortOverCurrentIndicatorChange: This bit is valid only if

overcurrent conditions are reported on a per-port basis. This bit is

set when Root Hub changes the PortOverCurrentIndicator bit. The

HCD writes logic 1 to clear this bit. Writing logic 0 has no effect.

0 — no change in PortOverCurrentIndicator

1 — PortOverCurrentIndicator has changed

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Table 35: HcRhPortStatus[1:2] register: bit description

Bit Symbol Description

18 PSSC PortSuspendStatusChange: This bit is set when the full resume

sequence has been completed. This sequence includes the 20 s

resume pulse, LS EOP, and 3 ms re-synchronization delay. The

HCD writes logic 1 to clear this bit. Writing logic 0 has no effect.

This bit is also cleared when ResetStatusChange is set.

0 — resume is not complete

1 — resume is complete

17 PESC PortEnableStatusChange: This bit is set when hardware events

cause the PortEnableStatus bit to be cleared. Changes from HCD

writes do not set this bit. The HCD writes logic 1 to clear this bit.

Writing logic 0 has no effect.

0 — no change in PortEnableStatus

1 — change in PortEnableStatus

16 CSC ConnectStatusChange: This bit is set whenever a connect or

disconnect event occurs. The HCD writes logic 1 to clear this bit.

Writing logic 0 has no effect. If CurrentConnectStatus is cleared

when a SetPortReset, SetPortEnable, or SetPortSuspend write

occurs, this bit is set to force the driver to re-evaluate the

connection status since these writes should not occur if the port is

disconnected.

…continued

0 — no change in CurrentConnectStatus

1 — change in CurrentConnectStatus

Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only

after a Root Hub reset to inform the system that the device is

connected. 15 to 10 - reserved 9 LSDA (read) LowSpeedDeviceAttached: This bit indicates the speed of

the device connected to this port. When set, a low-speed device is

connected to this port. When clear, a full-speed device is

connected to this port. This ﬁeld is valid only when the

CurrentConnectStatus is set.

0 — full-speed device attached

1 — low-speed device attached

(write) ClearPortPower: The HCD clears the PortPowerStatus bit

by writing logic 1 to this bit. Writing logic 0 has no effect.

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Table 35: HcRhPortStatus[1:2] register: bit description

Bit Symbol Description

8 PPS (read) PortPowerStatus: This bit reﬂects the port power status,

regardless of the type of power switching implemented. This bit is

cleared if an overcurrent condition is detected.

The HCD sets this bit by writing SetPortPower or SetGlobalPower.

The HCD clears this bit by writing ClearPortPower or

ClearGlobalPower. Which power control switches are enabled is

determined by PowerSwitchingMode.

In the global switching mode (PowerSwitchingMode = 0), only

Set/ClearGlobalPower controls this bit. In per-port power switching

(PowerSwitchingMode = 1), if the PortPowerControlMask[NDP] bit

for the port is set, only Set/ClearPortPower commands are

enabled. If the mask is not set, only Set/ClearGlobalPower

commands are enabled.

When port power is disabled, CurrentConnectStatus,

PortEnableStatus, PortSuspendStatus, and PortResetStatus

should be reset.

0 — port power is off

1 — port power is on

(write) SetPortPower: The HCD writes logic 1 to set the

PortPowerStatus bit. Writing logic 0 has no effect.

Remark: This bit always reads logic 1 if power switching is not

supported. 7 to 5 - reserved 4 PRS (read) PortResetStatus: When this bit is set by a write to

SetPortReset, port reset signaling is asserted. When reset is

completed, this bit is cleared when PortResetStatusChange is set.

This bit cannot be set if CurrentConnectStatus is cleared.

…continued

0 — port reset signal is not active

1 — port reset signal is active

(write) SetPortReset: The HCD sets the port reset signaling by

writing logic 1 to this bit. Writing logic 0 has no effect. If

CurrentConnectStatus is cleared, this write does not set

PortResetStatus but instead sets ConnectStatusChange. This

informs the driver that it attempted to reset a disconnected port. 3 POCI (read) PortOverCurrentIndicator: This bit is valid only when the

Root Hub is conﬁgured in such a way that overcurrent conditions

are reported on a per-port basis. If per-port overcurrent reporting

is not supported, this bit is set to logic 0. If cleared, all power

operations are normal for this port. If set, an overcurrent condition

exists on this port. This bit always reﬂects the overcurrent input

signal.

0 — no overcurrent condition

1 — overcurrent condition detected

(write) ClearSuspendStatus: The HCD writes logic 1 to initiate a

resume. Writing logic 0 has no effect. A resume is initiated only if

PortSuspendStatus is set.

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Table 35: HcRhPortStatus[1:2] register: bit description

Bit Symbol Description

2 PSS (read) PortSuspendStatus: This bit indicates whether the port is

suspended or in the resume sequence. It is set by a

SetSuspendState write and cleared when

PortSuspendStatusChange is set at the end of the resume

interval. This bit cannot be set if CurrentConnectStatus is cleared.

This bit is also cleared when PortResetStatusChange is set at the

end of the port reset or when the HC is placed in the USBResume

state. If an upstream resume is in progress, it is propagated to the

HC.

0 — port is not suspended

1 — port is suspended

(write) SetPortSuspend: The HCD sets the PortSuspendStatus

bit by writing logic 1 to this bit. Writing logic 0 has no effect. If

CurrentConnectStatus is cleared, this write action does not set

PortSuspendStatus; instead it sets ConnectStatusChange. This

informs the driver that it attempted to suspend a disconnected

port. 1 PES (read) PortEnableStatus: This bit indicates whether the port is

enabled or disabled. The Root Hub can clear this bit when an

overcurrent condition, disconnect event, switched-off power, or

operational bus error such as babble is detected. This change also

causes PortEnabledStatusChange to be set. The HCD sets this bit

by writing SetPortEnable and clears it by writing ClearPortEnable.

This bit cannot be set when CurrentConnectStatus is cleared. This

bit is also set at the completion of a port reset when

ResetStatusChange is set or port is suspended when

SuspendStatusChange is set.

…continued

0 — port is disabled

1 — port is enabled

(write) SetPortEnable: The HCD sets PortEnableStatus by writing

logic 1. Writing logic 0 has no effect. If CurrentConnectStatus is

cleared, this write does not set PortEnableStatus, but instead sets

ConnectStatusChange. This informs the driver that it attempted to

enable a disconnected port. 0 CCS (read) CurrentConnectStatus: This bit reﬂects the current state

of the downstream port.

0 — no device connected

1 — device connected

(write) ClearPortEnable: The HCD writes logic 1 to this bit to clear

the PortEnableStatus bit. Writing logic 0 has no effect.

CurrentConnectStatus is not affected by any write.

Remark: This bit always reads logic 1 when the attached device is

nonremovable (DeviceRemoveable[NDP]).

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10.4 HC DMA and interrupt control registers

10.4.1 HcHardwareConﬁguration register (R/W: 20H/A0H)

1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit should be used together with the register HcµPInterruptEnable to enable pin INT1.

2. Bits 4 and 3 are ﬁxed at logic 0 and logic 1 for the ISP1161A.

Code (Hex): 20 — read Code (Hex): A0 — write

Table 36: HcHardwareConﬁguration register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol reserved 2_Down

streamPort

15K

resistorsel

Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol EOTInput

Polarity

Reset 00101000 Access R/W R/W R/W R/W R/W R/W R/W R/W

DACKInput

Polarity

DREQOut

putPolarity

DataBusWidth[1:0] InterruptOut

Suspend

ClkNotStop

AnalogOC

Enable

putPolarity

reserved DACKMode

InterruptPi

nTrigger

InterruptPin

Enable

Table 37: HcHardwareConﬁguration register: bit description

Bit Symbol Description

15 to 13 - reserved 12 2_DownstreamPort15Kresistor

Sel

11 SuspendClkNotStop 0 — clock can be stopped

10 AnalogOCEnable 0 — use external OC detection. Digital input

9 - reserved 8 DACKMode 0 — normal operation.

7 EOTInputPolarity 0 — active LOW. Power-up value

6 DACKInputPolarity 0 — active LOW. Power-up value

0 — use external 15 kΩ resistors for downstream ports. Power-up value

1 — built-in resistors for downstream ports

1 — clock can not be stopped

1 — use on-chip OC detection. Analog input

DACK1 is used with read

and write signals. Power-up value

1 — reserved

1 — active HIGH

1 — reserved

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Table 37: HcHardwareConﬁguration register: bit description

Bit Symbol Description 5 DREQOutputPolarity 0 — active LOW

1 — active HIGH. Power-up value

4 to 3 DataBusWidth[1:0] 01 — 16 bits

Others — reserved

2 InterruptOutputPolarity 0 — active LOW. Power-up value

1 — active HIGH

1 InterruptPinTrigger 0 — interrupt is level-triggered. Power-up value

1 — interrupt is edge-triggered

0 InterruptPinEnable 0 — INT1 is disabled. Power-up value

1 — pin INT1 is enabled

…continued

10.4.2 HcDMAConﬁguration register (R/W: 21H/A1H)

Code (Hex): 21 — read Code (Hex): A1 — write

Table 38: HcDMAConﬁguration register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved BurstLen[1:0] DMA

Enable

Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

reserved DMACount

erSelect

ITL_ATL_

DataSelect

DMARead

WriteSelect

Table 39: HcDMAConﬁguration register: bit description

Bit Symbol Description

15 to 7 - reserved 6 to 5 BurstLen[1:0] 00 — single-cycle burst DMA

01 — 4-cycle burst DMA 10 — 8-cycle burst DMA 11 — reserved

4 DMAEnable 0 — DMA is terminated

1 — DMA is enabled

This bit will be reset to zero when DMA transfer is completed

3 - reserved

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Table 39: HcDMAConﬁguration register: bit description

Bit Symbol Description

2 DMACounter

Select

1 ITL_ATL_

DataSelect

0 DMARead

WriteSelect

0 — DMA counter not used. External EOT must be used 1 — Enables the DMA counter for DMA transfer.

HcTransferCounter register must be ﬁlled with non-zero values for DREQ1 to be raised after bit DMA Enable is set

0 — ITL buffer RAM selected for ITL data 1 — ATL buffer RAM selected for ATL data 0 — read from the HC FIFO buffer RAM 1 — write to the HC FIFO buffer RAM

10.4.3 HcTransferCounter register (R/W: 22H/A2H)

This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the number of bytes being read or written to the Isochronous Transfer List (ITL) or Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a DMA transfer, the number of bytes must be written into this register as well. However, for this counter to be read into the DMA counter, the HCD must set bit 2 of the HcDMAConﬁguration register. The counter value for ATL must not be greater than 1000H, and for ITL it must not be greater than 800H. When the byte count of the data transfer reaches this value, the HC will generate an internal EOT signal to set bit 2 (AllEOTInterrupt) of the HcµPInterrupt register, and also update the HcBufferStatus register.

…continued

Code (Hex): 22 — read Code (Hex): A2 — write

Table 40: HcTransferCounter register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol Counter value Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol Counter value Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 41: HcTransferCounter register: bit description

Bit Symbol Description

15 to 0 Counter

value

The number of data bytes to be read to or written from RAM

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10.4.4 HcµPInterrupt register (R/W: 24H/A4H)

All the bits in this register will be active on power-on reset. However, none of the active bits will cause an interrupt on the interrupt pin (INT1) unless they are set by the respective bits in the HcµPInterruptEnable register, and together with bit 0 of the HcHardwareConﬁguration register.

After this register (24H read) is read, the bits that are active will not be reset, until logic 1 is written to the bits in this register (A4H - write) to clear it. To clear all the enabled bits in this register, the HCD must write FFH to this register.

Code (Hex): 24 — read Code (Hex): A4 — write

Table 42: HcµPInterrupt register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved ClkReady HC

Suspended

Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

OPR_Reg reserved AllEOT

Interrupt

ATLInt SOFITLInt

Table 43: HcµPInterrupt register: bit description

Bit Symbol Description

15 to 7 - reserved 6 ClkReady 0 — no event

1 — clock is ready. After a wake-up is sent, there is a wait for clock ready. (Maximum is 1 ms, and typical is 160 µs)

5HC

Suspended

4 OPR_Reg 0 — no event

3 - reserved 2 AllEOT

Interrupt

0 — no event 1 — the HC has been suspended and no USB activity is sent from

the microprocessor for each ms. When the microprocessor wants to suspend the HC, the microprocessor must write to the HcControl register. And when all downstream devices are suspended, then the HC stops sending SOF; the HC is suspended by having the HcControl register written into.

1 — there are interrupts from HC side. Need to read HcControl and HcInterrupt registers to detect type of interrupt on the HC (if the HC requires the Operational register to be updated)

0 — no event 1 — implies that data transfer has been completed via PIO transfer

or DMA transfer. Occurrence of internal or external EOT will set this bit.

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Table 43: HcµPInterrupt register: bit description

Bit Symbol Description 1 ATLInt 0 — no event

1 — implies that the microprocessor must read ATL data from the

HC. This requires that the HcBufferStatus register must ﬁrst be read. The time for this interrupt depends on the number of clocks bit set for USB activities in each ms.

0 SOFITLInt 0 — no event

1 — implies that SOF indicates the 1 ms mark. The ITL buffer that the HC has handled must be read. To know the ITL buffer status, the HcBufferStatus register must ﬁrst be read. This is for the microprocessor to get ISO data to or from the HC. For more information, see the 6th paragraph in Section 9.5.

10.4.5 HcµPInterruptEnable register (R/W: 25H/A5H)

The bits 6:0 in this register are the same as those in the HcµPInterrupt register. They are used together with bit 0 of the HcHardwareConﬁguration register to enable or disable the bits in the HcµPInterrupt register.

At power-on, all bits in this register are masked with logic 0. This means no interrupt request output on the interrupt pin INT1 can be generated.

When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.

…continued

Code (Hex): 25 — read Code (Hex): A5 — write

Table 44: HcµPInterruptEnable register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved ClkReady HC

Suspended

Enable

Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 45: HcµPInterruptEnable register: bit description

Bit Symbol Description

15 to 7 - reserved 6 ClkReady 0 — power-up value

OPR

Interrupt

Enable

1 — enables Clkready interrupt

reserved EOT

Interrupt

Enable

ATL

Interrupt

Enable

SOF

Interrupt

Enable

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Table 45: HcµPInterruptEnable register: bit description

Bit Symbol Description

5HC

Suspended Enable

4 OPR

Interrupt Enable

3 - reserved 2EOT

Interrupt Enable

1ATL

Interrupt Enable

0 SOF

Interrupt Enable

0 — power-up value 1 — enables HC suspended interrupt. When the microprocessor

wants to suspend the HC, the microprocessor must write to the HcControl register. And when all downstream devices are suspended, then the HC stops sending SOF; the HC is suspended by having the HcControl register written into.

0 — power-up value 1 — enables the 32-bit Operational register’s interrupt (if the HC

requires the Operational register to be updated)

0 — power-up value 1 — enables the EOT interrupt which indicates an end of a

read/write transfer

0 — power-up value 1 — enables ATL interrupt. The time for this interrupt depends on

the number of clock bits set for USB activities in each ms.

0 — power-up value 1 — enables the interrupt bit due to SOF (for the microprocessor

DMA to get ISO data from the HC by ﬁrst accessing the HcDMAConﬁguration register)

…continued

10.5 HC miscellaneous registers

10.5.1 HcChipID register (R: 27H)

Read this register to get the ID of the ISP1161A silicon chip. The high byte stands for the product name (here 61H stands for ISP1161A). The low byte indicates the revision number of the product including engineering samples.

Code (Hex): 27 — read

Table 46: HcChipID register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol ChipID[15:8] Reset 01100001 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol ChipID[7:0] Reset 00100010 Access RRRRRRRR

Table 47: HcChipID register: bit description

Bit Symbol Description

15 to 0 ChipID[15:0] ISP1161A’s chip ID

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10.5.2 HcScratch register (R/W: 28H/A8H)

This register is for the HCD to save and restore values when required.

Code (Hex): 28 — read Code (Hex): A8 — write

Table 48: HcScratch register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol Scratch[15:8] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol Scratch[7:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 49: HcScratch register: bit description

Bit Symbol Description

15 to 0 Scratch[15:0] Scratch register value

10.5.3 HcSoftwareReset register (W: A9H)

This register provides a means for software reset of the HC. To reset the HC, the HCD must write a reset value of F6H to this register. Upon receiving the reset value, the HC resets all the registers except its buffer memory.

Code (Hex): A9 — write

Table 50: HcSoftwareReset register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol Reset[15:8] Reset 00000000 Access WWWWWWWW Bit 7 6 5 4 3 2 1 0 Symbol Reset[7:0] Reset 00000000 Access WWWWWWWW

Table 51: HcSoftwareReset register: bit description

Bit Symbol Description

15 to 0 Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the

registers except its buffer memory.

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10.6 HC buffer RAM control registers

10.6.1 HcITLBufferLength register (R/W: 2AH/AAH)

Write to this register to assign the ITL buffer size in bytes: ITL0 and ITL1 are assigned the same value. For example, if HcITLBufferLength register is set to 2 kbytes, then ITL0 and ITL1 would be allocated 2 kbytes each.

Must follow the formula: ATL buffer length + 2 × (ITL buffer size) ≤ 1000H (that is, 4 kbytes) where: ITL buffer size = ITL0 buffer length = ITL1 buffer length

Code (Hex): 2A — read Code (Hex): AA — write

Table 52: HcITLBufferLength register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol ITLBufferLength[15:8] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol ITLBufferLength[7:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 53: HcITLBufferLength register: bit description

Bit Symbol Description

15 to 0 ITLBufferLength[15:0] Assign ITL buffer length

10.6.2 HcATLBufferLength register (R/W: 2BH/ABH)

Write to this register to assign ATL buffer size.

Code (Hex): 2B — read Code (Hex): AB — write

Remark: The maximum total RAM size is 1000H (4096 in decimal) bytes. That

means ITL0 (length) + ITL1 (length) + ATL (length) ≤ 1000H bytes. For example, if ATL buffer length has been set to be 800H, then the maximum ITL buffer length can only be set as 400H.

Table 54: HcATLBufferLength register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol ATLBufferLength[15:8] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Bit 7 6 5 4 3 2 1 0 Symbol ATLBufferLength[7:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 55: HcATLBufferLength register: bit description

Bit Symbol Description

15 to 0 ATLBufferLength[15:0] Assign ATL buffer length

10.6.3 HcBufferStatus register (R: 2CH)

Code (Hex): 2C — read

Table 56: HcBufferStatus register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol reserved ATLBuffer

Done

Reset 00000000 Access RRRRRRRR

ITL1Buffer

Done

ITL0Buffer

Done

ATLBuffer

Full

ITL1Buffer

Full

ITL0Buffer

Full

Table 57: HcBufferStatus register: bit description

Bit Symbol Description

15 to 6 - reserved 5 ATLBuffer

Done

4 ITL1Buffer

Done

3 ITL0Buffer

Done

2 ATLBuffer

Full

1 ITL1Buffer

Full

0 ITL0Buffer

Full

0 — ATL Buffer not read by HC yet 1 — ATL Buffer read by HC 0 — ITL1 Buffer not read by HC yet 1 — ITL1 Buffer read by HC 0 — 1TL0 Buffer not read by HC yet 1 — 1TL0 Buffer read by HC 0 — ATL Buffer is empty 1 — ATL Buffer is full 0 — 1TL1 Buffer is empty 1 — 1TL1 Buffer is full 0 — ITL0 Buffer is empty 1 — ITL0 Buffer is full

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10.6.4 HcReadBackITL0Length register (R: 2DH)

This register’s value stands for the current number of data bytes inside an ITL0 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before reading back the ITL0 buffer RAM.

Code (Hex): 2D — read

Table 58: HcReadBackITL0Length register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol RdITL0BufferLength[15:8] Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol RdITL0BufferLength[7:0] Reset 00000000 Access RRRRRRRR

Table 59: HcReadBackITL0Length register: bit description

Bit Symbol Description

15 to 0 RdITL0BufferLength[15:0] The number of bytes for ITL0 data to be read back by

the microprocessor

10.6.5 HcReadBackITL1Length register (R: 2EH)

This register’s value stands for the current number of data bytes inside the ITL1 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before reading back the ITL1 buffer RAM.

Code (Hex): 2E — read

Table 60: HcReadBackITL1Length register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol RdITL1BufferLength[15:8] Reset 00000000 Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol RdITL1BufferLength[7:0] Reset 00000000 Access RRRRRRRR

Table 61: HcReadBackITL1Length register: bit description

Bit Symbol Description

15 to 0 RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by

the microprocessor

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10.6.6 HcITLBufferPort register (R/W: 40H/C0H)

This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte that comes from the ITL buffer RAM’s odd address.

Code (Hex): 40 — read Code (Hex): C0 — write

Table 62: HcITLBufferPort register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol DataWord[15:8] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol DataWord[7:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 63: HcITLBufferPort register: bit description

Bit Symbol Description

15 to 0 DataWord[15:0] read/write ITL buffer RAM’s two data bytes.

The HCD must set the byte count into the HcTransferCounter register and check the HcBufferStatus register before reading from or writing to the buffer. The HCD must write the command (40H for read, C0H for write) once only, and then read or write both bytes of the data word. After every read/write, the pointer of ITL buffer RAM will be automatically increased by two to point to the next data word until it reaches the value of HcTransferCounter register; otherwise, an internal EOT signal is not generated to set the bit 2 (AllEOTInterrupt) of the HcµPInterrupt register and update the HcBufferStatus register.

The HCD must take care of the fact that the internal buffer RAM is organized in bytes. The HCD must write the byte count into the HcTransferCounter register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 data word).

10.6.7 HcATLBufferPort register (R/W: 41H/C1H)

This is the ATL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the Acknowledged Transfer List (ATL)bufferRAM’s odd address. Bits 7:0 contain the data byte that comes from the ATL buffer RAM’s even address.

Code (Hex): 41 — read Code (Hex): C1 — write

Table 64: HcATLBufferPort register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol DataWord[15:8] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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ISP1161A

Full-speed USB single-chip host and device controller

Bit 7 6 5 4 3 2 1 0 Symbol DataWord[7:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 65: HcATLBufferPort register: bit description

Bit Symbol Description

15 to 0 DataWord[15:0] read/write ATL buffer RAM’s two data bytes.

The HCD must set the byte count into the HcTransferCounter register and check the HcBufferStatus register before reading from or writing to the buffer. The HCD must write the command (41H for read, C1H for write) once only, and then read or write both bytes of the data word. After every read/write, the pointer of ATL buffer RAM will be automatically increased by two to point to the next data word until it reaches the value of HcTransferCounter register; otherwise, an internal EOT signal is not generated to set the bit 2 (AllEOTInterrupt) of the HcµPInterrupt register and update the HcBufferStatus register.

The HCD must take care of the difference: the internal buffer RAM is organized in bytes, so the HCD must write the byte count into the HcTransferCounter register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 data word).

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11. USB device controller (DC)

The Device Controller (DC) in the ISP1161A is based on the Philips ISP1181B USB Full-Speed Interface Device IC. The functionality, commands, and register sets are the same as ISP1181B in 16-bit bus mode. If there are any differences between the ISP1181B and ISP1161A data sheets, in terms of the DC functionality,the ISP1161A data sheet supersedes content in the ISP1181B data sheet.

In general the DC in an ISP1161A provides 16 endpoints for USB device implementation. Each endpoint can be allocated an amount of RAM space in the on-chip Ping-Pong buffer RAM.

Remark: The Ping-Pong buffer RAM for the DC is independent of the buffer RAM in the HC.

When the buffer RAM is full, the DC will transfer the data in the buffer RAM to the USB bus. When the buffer RAM is empty, an interrupt is generated to notify the microprocessor to feed in the data. The transfer of data between the microprocessor and the DC can be done in Programmed I/O (PIO) mode or in DMA mode.

ISP1161A

Full-speed USB single-chip host and device controller

11.1 DC data transfer operation

The following session explains how the DC of an ISP1161A handles an IN data transfer and an OUT data transfer. In the Device mode, ISP1161A acts as a USB device: an IN data transfer means transfer from ISP1161A to an external USB Host (through the upstream port) and an OUT transfer means transfer from external USB Host to ISP1161A.

11.1.1 IN data transfer

• The arrival of the IN token is detected by the SIE by decoding the PID.

• The SIE also checks for the device number and endpoint number and veriﬁes

whether they are acceptable.

• If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus

register. If the endpoint is full, the contents of the FIFO are sent during the data phase, otherwise a Not Acknowledge (NAK) handshake is sent.

• After the data phase, the SIE expects a handshake (ACK) from the host (except for

ISO endpoints).

• On receiving the handshake (ACK), the SIE updates the contents of the

DcEndpointStatus register and the DcInterrupt register,which in turn generates an interrupt to the microprocessor.ForISO endpoints, the interrupt register is updated as soon as data is sent because there is no handshake phase.

• On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will

know which endpoint has generated the interrupt and reads the contents of the corresponding DcEndpointStatus register. If the buffer is empty,it ﬁlls up the buffer, so that data can be sent by the SIE at the next IN token phase.

11.1.2 OUT data transfer

• The arrival of the OUT token is detected by the SIE by decoding the PID.

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• The SIE also checks for the device number and endpoint number and veriﬁes

• If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus

• After the data phase, the SIE sends a handshake (ACK)to the host (except for ISO

• The SIE updates the contents of the DcEndpointStatus register and the

• On receiving interrupt, the microprocessor reads the DcInterrupt register. It will

11.2 Device DMA transfer

ISP1161A

Full-speed USB single-chip host and device controller

whether they are acceptable.

register. If the endpoint is empty, the data from USB is stored to FIFO during the data phase, otherwise a NAK handshake is sent.

endpoints).

DcInterrupt register, which in turn generates an interrupt to the microprocessor. For ISO endpoints, the interrupt register is updated as soon as data is received because there is no handshake phase.

know which endpoint has generated the interrupt and reads the content of the corresponding DcEndpointStatus register. If the buffer is full, it empties the buffer, so that data can be received by the SIE at the next OUT token phase.

11.2.1 DMA for IN endpoint (internal DC to external USB host)

When the internal DMA handler is enabled and at least one buffer (Ping or Pong) is free, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus. As soon as it has access, it asserts the DACK2 line and starts writing data. The burst length is programmable. When the number of bytes equal to the burst length has been written, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the DACK2 line and releases the bus. At that moment the whole cycle restarts for the next burst.

When the buffer is full, the DREQ2 line will be de-asserted and the buffer is validated (which means that it will be sent to the host when the next IN token comes in). When the DMA transfer is terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated when any of the following conditions are met:

• the DMA count is complete

• DMAEN = 0

• the DMA controller asserts EOT.

11.2.2 DMA for OUT endpoint (external USB host to internal DC)

When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus, and as soon as it has access, it asserts the DACK2 line and starts reading the data. The burst length is programmable. When the number of bytes equal to the burst length has been read, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the DACK2 line and releases the bus. At that moment the whole cycle restarts for the next burst. When all data are read, the DREQ2 line will be de-asserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in).

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A DMA transfer is terminated when any of the following conditions are met:

• The DMA count is complete

• DMAEN = 0

• The DMA controller asserts EOT.

When the DMA transfer is terminated, the buffer is also cleared (even if the data is not completely read) and the DMA handler is disabled automatically. For the next DMA transfer, the DMA controller as well as the DMA handler must be re-enabled.

11.3 Endpoint descriptions

11.3.1 Endpoints with programmable FIFO size

Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication ﬂow between the host and the device. At design time each endpoint is assigned a unique number (endpoint identiﬁer, see Table 66). The combination of the device address (given by the host during enumeration), the endpoint number and the transfer direction allows each endpoint to be uniquely referenced.

ISP1161A

Full-speed USB single-chip host and device controller

The DC has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 conﬁgurable endpoints, which can be individually deﬁned as interrupt/bulk/isochronous, IN or OUT. Each enabled endpoint has an associated FIFO, which can be accessed either via the Programmed I/O interface or via DMA.

11.3.2 Endpoint access

Table 66 lists the endpoint access modes and programmability. All endpoints support

I/O mode access. Endpoints 1 to 14 also support DMA access. DC FIFO DMA access is selected and enabled via bits EPIDX[3:0] and DMAEN of the DcDMAConﬁguration register. A detailed description of the DC DMA operation is given in Section 12.

Table 66: Endpoint access and programmability

Endpoint identiﬁer

0 64 (ﬁxed) no yes no control OUT 0 64 (ﬁxed) no yes no control IN 1 to 14 programmable supported supported supported programmable

[1] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1161A transmits); OUT: output from the USB host (ISP1161A receives). The data ﬂow direction is

determined by bit EPDIR in the DcEndpointConﬁguration register; see Section 13.1.1

FIFO size (bytes)

[1]

Double buffering

I/O mode access

DMA mode access

Endpoint type

[2]

11.3.3 Endpoint FIFO size

The size of the FIFO determines the maximum packet size that the hardware can support for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO storage, disabled endpoints have zero bytes. Table 67 lists the programmable FIFO sizes.

The following bits in the DcEndpointConﬁguration register (ECR) affect FIFO allocation:

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• Endpoint enable bit (FIFOEN)

• Size bits of an enabled endpoint (FFOSZ[3:0])

• Isochronous bit of an enabled endpoint (FFOISO).

Remark: Register changes that affect the allocation of the shared FIFO storage

among endpoints must not be made while valid data is present in any FIFO of the enabled endpoints. Such changes will render all FIFO contents undeﬁned.

Table 67: Programmable FIFO size

FFOSZ[3:0] Non-isochronous Isochronous

0000 8 bytes 16 bytes 0001 16 bytes 32bytes 0010 32 bytes 48bytes 0011 64 bytes 64bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes

ISP1161A

Full-speed USB single-chip host and device controller

Each programmable FIFO can be conﬁgured independently via its ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes (512 bytes for non-isochronous FIFOs).

Table 68 shows an example of a conﬁguration ﬁtting in the maximum available space

of 2462 bytes. The total number of logical bytes in the example is 1311. The physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user.

Table 68: Memory conﬁguration example

Physical size (bytes)

64 64 control IN (64 byte ﬁxed) 64 64 control OUT (64 byte ﬁxed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt OUT 16 16 16-byte interrupt IN 128 64 double-buffered 64-byte bulk OUT 128 64 double-buffered 64-byte bulk IN

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Logical size (bytes)

Endpoint description

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11.3.4 Endpoint initialization

In response to the standard USB request, Set Interface, the ﬁrmware must program all 16 ECRs of the ISP1161A’s DC in sequence (see Table 66), whether the endpoints are enabled or not. The hardware will then automatically allocate FIFO storage space.

If all endpoints have been conﬁgured successfully, the ﬁrmware must return an empty packet to the control IN endpoint to acknowledge success to the host. If there are errors in the endpoint conﬁguration, the ﬁrmware must stall the control IN endpoint.

When reset by hardware or via the USB bus, the ISP1161A’s DC disables all endpoints and clears all ECRs, except for the control endpoint which is ﬁxed and always enabled.

Endpoint initialization can be done at any time; however, it is valid only after enumeration.

11.3.5 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (EPn) of the DcInterrupt register will be set by the SIE. The ﬁrmware then responds to the interrupt and selects the endpoint for processing.

ISP1161A

Full-speed USB single-chip host and device controller

The endpoint interrupt bit will be cleared by reading the DcEndpointStatus register (ESR). The ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and packet data can be read from ISP1161A’s DC using the Read Buffer command. When the whole packet has been read, the ﬁrmware sends a Clear Buffer command to enable the reception of new packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written to ISP1161A’sDC using the WriteBuffercommand. When the whole packethas been written to the buffer, the ﬁrmware sends a Validate Buffer command to enable data transmission to the host.

11.3.6 Special actions on control endpoints

Control endpoints require special ﬁrmware actions. The arrival of a SETUP packet ﬂushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microcontroller needs to re-enable these commands by sending an Acknowledge Setup command.

This ensures that the last SETUP packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the SETUP packet.

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11.4 Suspend and resume

11.4.1 Suspend conditions

The ISP1161A DC detects a USB suspend status when a constant idle state is present on the USB bus for more than 3 ms.

The bus-powered devices that are suspended must not consume more than 500 µA of current. This is achieved by shutting down power to system components or supplying them with a reduced voltage.

The steps leading up to suspend status are as follows:

1. On detecting a wakeup-to-suspend transition, the ISP1161A DC sets

2. When the ﬁrmware detects a suspend condition, it must prepare all system

3. In the interrupt service routine, the ﬁrmware must check the current status of the

4. Tomeet the suspend current requirements for a bus-powered device, the internal

5. When the ﬁrmware has set and cleared bit GOSUSP in the DcMode register, the

ISP1161A

Full-speed USB single-chip host and device controller

bit SUSPND in the DcInterrupt register. This will generate an interrupt if bit IESUSP in the DcInterruptEnable register is set.

components for the suspend state:

a. All signals connected to the ISP1161A DC must enter appropriate states to

meet the power consumption requirements of the suspend state.

b. All input pins of the ISP1161A DC must have a CMOS LOW or HIGH level.

USB bus. When bit BUSTATUS in the DcInterrupt register is logic 0, the USB bus has left the suspend mode and the process must be aborted. Otherwise, the next step can be executed.

clocks must be switched off by clearing bit CLKRUN in the DcHardwareConﬁguration register.

ISP1161A enters the suspend state. In powered-off application, the ISP1161A DC asserts output SUSPEND and switches off the internal clocks after 2 ms.

Figure 38 shows a typical timing diagram.

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ISP1161A

Full-speed USB single-chip host and device controller

USB BUS

INT_N

GOSUSP

WAKEUP

SUSPEND

Fig 38. Suspend and resume timing.

In Figure 38:

> 3 ms

suspend interrupt

> 5 ms

idle state

1.8 ms to 2.2 ms

10 ms

K-state

resume

interrupt

004aaa359

0.5 ms to 3.5 ms

• A: indicates the point at which the USB bus enters the idle state.

• B: indicates resume condition, which can be a 20 ms K-state on the USB bus, a

HIGH level on pin D_WAKEUP, or a LOW level on pin CS.

• C: indicates remote wake-up. The ISP1161A will drive a K-state on the USB bus

for 10 ms after pin D_WAKEUP goes HIGH or pin CS goes LOW.

• D: after detecting the suspend interrupt, set and clear bit GOSUSP in the DcMode

Powered-off application: Figure 39 shows a typical bus-powered modem

application using the ISP1161A. The SUSPEND output switches off power to the microcontroller and other external circuits during the suspend state. The ISP1161A DC is woken up through the USB bus (global resume) or by the ring detection circuit on the telephone line.

USB

BUS

DP DM

ISP1161A

BUS

SUSPEND

WAKEUP

8031

RST

RING DETECTION

LINE

004aaa674

Fig 39. SUSPEND and WAKEUP signals in a powered-off modem application.

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11.4.2 Resume conditions

A wake-up from the suspend state is initiated either by the USB host or by the application:

• USB host: drives a K-state on the USB bus (global resume)

• Application: remote wake-up through a HIGH level on input WAKEUP or a LOW

The steps of a wake-up sequence are as follows:

1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the

2. The SUSPEND output is deasserted, and bit RESUME in the DcInterrupt register

3. Maximum 15 ms after starting the wake-up sequence, the ISP1161A DC

4. In case of a remote wake-up, the ISP1161A DC drives a K-state on the USB bus

5. Following the deassertion of output SUSPEND,the application restores itself and

6. After wake-up, the internal registers of the ISP1161A DC are write-protected to

ISP1161A

Full-speed USB single-chip host and device controller

level on input CS, if enabled using bit WKUPCS in the DcHardwareConﬁguration register. Wake-up on CS will work only if V

clock signals are routed to all internal circuits of the ISP1161A.

is set. This will generate an interrupt if bit IERESM in the DcInterruptEnable register is set.

resumes its normal functionality.

for 10 ms.

other system components to the normal operating mode.

prevent corruption by inadvertent writing during power-up of external components. The ﬁrmware must send an Unlock Device command to the ISP1161A DC to restore its full functionality.

is present.

BUS

11.4.3 Control bits in suspend and resume

Table 69: Summary of control bits

DcInterrupt SUSPND a transition from awake to the suspend state was detected

BUSTATUS monitors USB bus status (logic 1 = suspend); used when

interrupt is serviced

RESUME a transition from suspend to the resume state was detected

DcInterrupt Enable

DcMode SOFTCT enables SoftConnect pull-up resistor to USB bus

DcHardware Conﬁguration

DcUnlock all sending data AA37H unlocks the internal registers for

IESUSP enables output INT to signal the suspend state IERESM enables output INT to signal the resume state

GOSUSP a HIGH-to-LOW transition enables the suspend state EXTPUL selects internal (SoftConnect) or external pull-up resistor WKUPCS enables wake-up on LOW level of input PWROFF selects powered-off mode during the suspend state

writing after a resume

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12. DC DMA transfer

Direct Memory Access (DMA) is a method to transfer data from one location to another in a computer system, without intervention of the Central Processor Unit (CPU). Many different implementations of DMA exist. The ISP1161A DC supports two methods:

• 8237 compatible mode: based on the DMA subsystem of the IBM personal

• DACK-only mode: based on the DMA implementation in some embedded RISC

ISP1161A’s DC supports DMA transfer for all 14 conﬁgurable endpoints (see

Table 66). Only one endpoint at a time can be selected for DMA transfer. The DMA

operation of ISP1161A’s DC can be interleaved with normal I/O mode access to other endpoints.

The following features are supported:

ISP1161A

Full-speed USB single-chip host and device controller

computers (PC, AT and all its successors and clones); this architecture uses the Intel 8237 DMA controller and has separate address spaces for memory and I/O

processors, which has a single address space for both memory and I/O.

• Single-cycle or burst transfers (up to 16 bytes per cycle)

• Programmable transfer direction (read or write)

• Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,

short/empty packet

• Programmable signal levels on pins DREQ2 and EOT.

12.1 Selecting an endpoint for DMA transfer

The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DcDMAConﬁguration register, as shown in Table 70. The transfer direction (read or write) is automatically set by bit EPDIR in the associated ECR, to match the selected endpoint type (OUT endpoint: read; IN endpoint: write).

Asserting input DACK2 automatically selects the endpoint speciﬁed in the DcDMAConﬁguration register, regardless of the current endpoint used for I/O mode access.

Table 70: Endpoint selection for DMA transfer

Endpoint identiﬁer

1 0010 OUT: read IN: write 2 0011 OUT: read IN: write 3 0100 OUT: read IN: write 4 0101 OUT: read IN: write 5 0110 OUT: read IN: write 6 0111 OUT: read IN: write 7 1000 OUT: read IN: write 8 1001 OUT: read IN: write 9 1010 OUT: read IN: write

EPIDX[3:0] Transfer direction

EPDIR = 0 EPDIR = 1

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ISP1161A

Full-speed USB single-chip host and device controller

Table 70: Endpoint selection for DMA transfer

Endpoint

EPIDX[3:0] Transfer direction

identiﬁer

10 1011 OUT: read IN: write 11 1100 OUT: read IN: write 12 1101 OUT: read IN: write 13 1110 OUT: read IN: write 14 1111 OUT: read IN: write

12.2 8237 compatible mode

The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the DcHardwareConﬁguration register (see Table 82). The pin functions for this mode are shown in Table 71.

Table 71: 8237 compatible mode: pin functions

Symbol Description I/O Function

DREQ2 DC’s DMA request O ISP1161A’s DC requests a DMA transfer DACK2 DC’s DMA

acknowledge EOT end of transfer I DMA controller terminates the transfer RD read strobe I instructs ISP1161A’s DC to put data on

WR write strobe I instructs ISP1161A’s DC to get data from

…continued

EPDIR = 0 EPDIR = 1

I DMA controller conﬁrms the transfer

the bus

The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA controller. It operates as a ‘ﬂy-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1161A’s DC in 8237 compatible DMA mode is given in Figure 40.

The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA (Hold Acknowledge). The bus operation is controlled via MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).

D0 to D15

ISP1161A

DEVICE

CONTROLLER

DREQ2

DACK2

RAM

Fig 40. ISP1161A’s device controller in the 8237 compatible DMA mode.

MEMR MEMW

DMA

CONTROLLER

8237

DREQ HRQ DACK

IOR IOW

HLDA

CPU

HRQ HLDA

004aaa093

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The following example shows the steps which occur in a typical DMA transfer:

1. ISP1161A’s DC receives a data packet in one of its endpoint FIFOs; the packet

2. ISP1161A’s DC asserts the DREQ2 signal requesting the 8237 for a DMA

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places the bus control

5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR

6. The 8237 asserts DACK to inform ISP1161A’s DC that it will start a DMA transfer.

7. ISP1161A’s DC now places the word to be transferred on the data bus lines,

8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This

9. ISP1161A’s DC de-asserts the DREQ2 signal to indicate to the 8237 that DMA is

10. The 8237 de-asserts the DACK output indicating that ISP1161A’s DC must stop

11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the

12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating

ISP1161A

Full-speed USB single-chip host and device controller

must be transferred to memory address 1234H.

transfer.

signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and asserts HLDA to inform the 8237 that it has control of the bus.

control signals.

because its RD signal was asserted by the 8237.

latches and stores the word at the desired memory location. It also informs ISP1161A’s DC that the data on the bus lines has been transferred.

no longer needed. In Single cycle mode this is done after each word, in Burst mode following the last transferred word of the DMA cycle.

placing data on the bus.

address lines in three-state and de-asserts the HRQ signal, informing the CPU that it has released the bus.

the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the CPU resumes the execution of instructions.

For a typical bulk transfer the above process is repeated, once for each byte. After each byte the address register in the DMA controller is incremented and the byte counter is decremented. When using 16-bit DMA the number of transfers is 32, and address incrementing and byte counter decrementing is done by 2 for each word.

12.3 DACK-only mode

The DACK-only DMA mode is selected by setting bit DAKOLY in the DcHardwareConﬁguration register (see Table 82). The pin functions for this mode are shown in Table 72. A typical example of ISP1161A’s DC in DACK-only DMA mode is given in Figure 41.

Table 72: DACK-only mode: pin functions

Symbol Description I/O Function

DREQ2 DC’s DMA request O ISP1161A DC requests a DMA transfer DACK2 DC’s DMA

acknowledge

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I DMA controller conﬁrms the transfer;

also functions as data strobe

Philips Semiconductors

ISP1161A

Full-speed USB single-chip host and device controller

Table 72: DACK-only mode: pin functions

Symbol Description I/O Function

EOT End-Of-Transfer I DMA controller terminates the transfer RD read strobe I not used WR write strobe I not used

…continued

In DACK-only mode ISP1161A’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes.

ISP1161A

DEVICE

CONTROLLER

DREQ2 DACK2

D0 to D15

RAM

DMA

CONTROLLER

DREQ DACK

HRQ

HLDA

CPU

HRQ HLDA

004aaa094

Fig 41. ISP1161A’s device controller in DACK-only DMA mode.

12.4 End-Of-Transfer conditions

12.4.1 Bulk endpoints

A DMA transfer to/from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConﬁguration register, see Table 86):

• An external End-Of-Transfer signal occurs on input EOT

• The DMA transfer completes as programmed in the DcDMACounter register

(CNTREN = 1)

• A short packet is received on an enabled OUT endpoint (SHORTP = 1)

• DMA operation is disabled by clearing bit DMAEN.

External EOT: When reading from an OUT endpoint, an external EOT will stop the

DMA operation and clear any remaining data in the current FIFO. For a doublebuffered endpoint the other (inactive) buffer is not affected.

When writing to an IN endpoint, an EOT will stop the DMA operation and the data packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to the USB host at the next IN token.

DcDMACounter register: An EOT from the DcDMACounter register is enabled by

setting bit CNTREN in the DcDMAConﬁguration register. The ISP1161A has a 16-bit DcDMACounter register,which speciﬁes the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the valuefrom

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the DcDMACounter register. When the internal counter completes the transfer as programmed in the DcDMACounter, an EOT condition is generated and the DMA operation stops.

Short packet: Normally, the transfer byte count must be set via a control endpoint

before any DMA transfertakes place. When a short packet has been enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet in the data. This mechanism permits the use of a fully autonomous data transfer protocol.

When reading from an OUT endpoint, reception of a short packet at an OUT token will stop the DMA operation after transferring the data bytes of this packet.

Table 73: Summary of EOT conditions for a bulk endpoint

EOT condition OUT endpoint IN endpoint

EOT input EOT is active EOT is active DcDMACounter register transfer completes as

Short packet short packet is received and

DMAEN bit in DcDMAConﬁguration register

ISP1161A

Full-speed USB single-chip host and device controller

transfer completes as programmed in the DcDMACounter register

transferred DMAEN = 0

[1]

programmed in the

DcDMACounter register

counter reaches zero in the

middle of the buffer

DMAEN = 0

[1]

[1] The DMA transfer stops. However, no interrupt is generated.

12.4.2 Isochronous endpoints

A DMA transfer to/from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConﬁguration register, see

Table 86):

• An external End-Of-Transfer signal occurs on input EOT

• The DMA transfer completes as programmed in the DcDMACounter register

(CNTREN = 1)

• An End-Of-Packet (EOP) signal is detected

• DMA operation is disabled by clearing bit DMAEN.

Table 74: Recommended EOT usage for isochronous endpoints

EOT condition OUT endpoint IN endpoint

EOT input active do not use preferred DMA Counter register zero do not use preferred End-Of-Packet preferred do not use

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13. DC commands and registers

The functions and registers of ISP1161A’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in Table 75.

A complete access consists of two phases:

1. Command phase: when address bit A0 = 1, the DC interprets the data on the lower byte of the bus (bits D7 to D0) as a command code. Commands without a data phase are executed immediately.

2. Data phase (optional): when address bit A0 = 0, the DC transfers the data on the bus to or from a register or endpoint FIFO. Multi-byte registers are accessed least signiﬁcant byte/word ﬁrst.

As the ISP1161A DC’s data bus is 16 bits wide:

• The upper byte (bits D15 to D8) in command phase, or the undeﬁned byte in data

phase and is ignored.

• The access of registers is word-aligned: byte access is not allowed.

• If the packet length is odd, the upper byte of the last word in an IN endpoint buffer

is not transmitted to the host. When reading from an OUT endpoint buffer, the upper byte of the last word must be ignored by the ﬁrmware. The packet length is stored in the ﬁrst 2 bytes of the endpoint buffer.

ISP1161A

Full-speed USB single-chip host and device controller

Table 75: DC command and register summary

Name Destination Code (Hex) Transaction

Initialization commands

Write Control OUT Conﬁguration DcEndpointConﬁguration register

endpoint 0 OUT

Write Control IN Conﬁguration DcEndpointConﬁguration register

endpoint 0 IN

Write Endpoint n Conﬁguration (n = 1 to 14)

Read Control OUT Conﬁguration DcEndpointConﬁguration register

Read Control IN Conﬁguration DcEndpointConﬁguration register

Read Endpoint n Conﬁguration (n = 1 to 14)

Write/Read Device Address DcAddress register B6/B7 write/read 1 word Write/Read DcMode register DcMode register B8/B9 write/read 1 word Write/Read Hardware Conﬁguration DcHardwareConﬁguration register BA/BB write/read 1 word Write/Read DcInterruptEnable

register Write/Read DMA Conﬁguration DcDMAConﬁguration register F0/F1 write/read 1 word Write/Read DMA Counter DcDMACounter register F2/F3 write/read 1 word Reset Device resets all registers F6 -

DcEndpointConﬁguration register endpoint 1 to 14

endpoint 0 OUT

endpoint 0 IN DcEndpointConﬁguration register

endpoint 1 to 14

DcInterruptEnable register C2/C3 write/read 2 words

20 write 1 word

21 write 1 word

22 to 2F write 1 word

30 read 1 word

31 read 1 word

32 to 3F read 1 word

[1]

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Full-speed USB single-chip host and device controller

Table 75: DC command and register summary

…continued

Name Destination Code (Hex) Transaction

Data ﬂow commands

Write Control OUT Buffer illegal: endpoint is read-only (00) Write Control IN Buffer FIFO endpoint 0 IN 01 N ≤ 64 bytes Write Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14 (IN endpoints only)

02 to 0F isochronous: N ≤ 1023 bytes

interrupt/bulk: N ≤ 64 bytes Read Control OUT Buffer FIFO endpoint 0 OUT 10 N ≤ 64 bytes Read Control IN Buffer illegal: endpoint is write-only (11) Read Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14 (OUTendpoints only)

12 to 1F isochronous:

N ≤ 1023 bytes

interrupt/bulk: N ≤ 64 bytes Stall Control OUT Endpoint Endpoint 0 OUT 40 Stall Control IN Endpoint Endpoint 0 IN 41 Stall Endpoint n

Endpoint 1 to 14 42 to 4F -

(n = 1 to 14) Read Control OUT Status DcEndpointStatus register

50 read 1 word

endpoint 0 OUT

Read Control IN Status DcEndpointStatus register

51 read 1 word

endpoint 0 IN

Read Endpoint n Status (n = 1 to 14)

Validate Control OUT Buffer illegal: IN endpoints only Validate Control IN Buffer FIFO endpoint 0 IN Validate Endpoint n Buffer

(n = 1 to 14)

DcEndpointStatus register n endpoint 1 to 14

[2]

FIFO endpoint 1 to 14 (IN endpoints only)

[2]

52 to 5F read 1 word

(60) 61 none 62 to 6F none

Clear Control OUT Buffer FIFO endpoint 0 OUT 70 none Clear Control IN Buffer illegal Clear Endpoint n Buffer

(n = 1 to 14)

[3]

FIFO endpoint 1 to 14 (OUT endpoints only)

(71) 72 to 7F none

[3]

Unstall Control OUT Endpoint Endpoint 0 OUT 80 Unstall Control IN Endpoint Endpoint 0 IN 81 Unstall Endpoint n

Endpoint 1 to 14 82 to 8F -

(n = 1 to 14) Check Control OUT Status

[4]

DcEndpointStatusImage register

D0 read 1 word

endpoint 0 OUT

Check Control IN Status

[4]

DcEndpointStatusImage register

D1 read 1 word

endpoint 0 IN

Check Endpoint n Status (n = 1 to 14)

[4]

DcEndpointStatusImage register n endpoint 1 to 14

D2 to DF read 1 word

Acknowledge Setup Endpoint 0 IN and OUT F4 none

General commands

Read Control OUT Error Code DcErrorCode register

A0 read 1 word

endpoint 0 OUT

Read Control IN Error Code DcErrorCode register

A1 read 1 word

endpoint 0 IN

[1]

[6]

[5]

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ISP1161A

Full-speed USB single-chip host and device controller

Table 75: DC command and register summary

Name Destination Code (Hex) Transaction

Read Endpoint n Error Code (n = 1 to 14)

Unlock Device all registers with write access B0 write 1 word Write/Read DcScratch register DcScratch register B2/B3 write/read 1 word Read Frame Number DcFrameNumber register B4 read 1 word Read Chip ID DcChipID register B5 read 1 word Read DcInterrupt register DcInterrupt register C0 read 2 words

[1] With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2. [2] Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161A’s DC. [3] Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161A’s DC. [4] Reads a copy of the DcStatus register: executing this command does not clear any status bits or interrupt bits. [5] When accessing an 8-bit register in 16-bit mode, the upper byte is invalid. [6] During isochronous transfer in 16-bit mode, because N ≤ 1023, the ﬁrmware must take care of the upper byte.

DcErrorCode register endpoint 1 to 14

…continued

A2 to AF read 1 word

[1] [5]

13.1 Initialization commands

Initialization commands are used during the enumeration process of the USB network. These commands are used to conﬁgure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1161A’s DC and to perform a device reset.

13.1.1 DcEndpointConﬁguration register (R/W: 30H–3FH/20H–2FH)

This command is used to access the DcEndpointConﬁguration register (ECR) of the target endpoint. It deﬁnes the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The register bit allocation is shown in Table 76. A bus reset will disable all endpoints.

The allocation of FIFO memory only takes place after all 16 endpoints have been conﬁgured in sequence (from endpoint 0 OUT to endpoint 14). Although the control endpoints have ﬁxed conﬁgurations, they must be included in the initialization sequence and be conﬁgured with their default values (see Table 66). Automatic FIFO allocation starts when endpoint 14 has been conﬁgured.

Remark: If any change is made to an endpoint conﬁguration which affects the allocated memory (size, enable/disable), the FIFO memory contents of all endpoints becomes invalid. Therefore, all valid data must be removed from enabled endpoints before changing the conﬁguration.

Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14) Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14) Transaction — write/read 1 word

Table 76: DcEndpointConﬁguration register: bit allocation

Bit 7 6 5 4 3 2 1 0 Symbol FIFOEN EPDIR DBLBUF FFOISO FFOSZ[3:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Table 77: DcEndpointConﬁguration register: bit description

Bit Symbol Description

7 FIFOEN Logic 1 indicates an enabled FIFO with allocated memory.

6 EPDIR This bit deﬁnes the endpoint direction (0 = OUT, 1 = IN); it also

5 DBLBUF Logic 1 indicates that this endpoint has double buffering. 4 FFOISO Logic 1 indicates an isochronous endpoint. Logic 0 indicates a

3 to 0 FFOSZ[3:0] Selects the FIFO size according to Table 67

13.1.2 DcAddress register (R/W: B7H/B6H)

This command is used to set the USB assigned address in the DcAddress register and enable the USB device. The DcAddress register bit allocation is shown in

Table 78.

A USB bus reset sets the device address to 00H (internally) and enables the device. The value of the DcAddress register (accessible by the microcontroller) is not altered by the bus reset. In response to the standard USB request, Set Address, the ﬁrmware must issue a Write Device Address command, followed by sending an empty packet to the host. The new device address is activated when the host acknowledges the empty packet.

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Full-speed USB single-chip host and device controller

Logic 0 indicates a disabled FIFO (no bytes allocated).

determines the DMA transfer direction (0 = read, 1 = write).

bulk or interrupt endpoint.

Code (Hex): B6/B7 — write/read DcAddress register Transaction — write/read 1 word

Table 78: DcAddress register: bit allocation

Bit 7 6 5 4 3 2 1 0 Symbol DEVEN DEVADR[6:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 79: DcAddress register: bit description

Bit Symbol Description

7 DEVEN Logic 1 enables the device. 6 to 0 DEVADR[6:0] This ﬁeld speciﬁes the USB device address.

13.1.3 DcMode register (R/W: B9H/B8H)

This command is used to access the ISP1161A’s DcMode register, which consists of 1 byte (for bit allocation: see Table 79). In 16-bit bus mode the upper byte is ignored.

The DcMode register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.

Code (Hex): B8/B9 — write/read Mode register Transaction — write/read 1 word

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Full-speed USB single-chip host and device controller

Table 80: DcMode register: bit allocation

Bit 7 6 5 4 3 2 1 0 Symbol DMAWD reserved GOSUSP reserved INTENA DBGMOD reserved SOFTCT Reset 0 Access R/W R/W R/W R/W R/W R/W R/W R/W

[1] Unchanged by a bus reset.

[1]

0000

Table 81: DcMode register: bit description

Bit Symbol Description

7 DMAWD Logic 1 selects 16-bit DMA bus width (bus conﬁguration

modes 0 and 2). Logic 0 selects 8-bit DMA bus width. Bus reset

value: unchanged. 6 - reserved 5 GOSUSP Writing logic 1 followed by logic 0 will activate ‘suspend’ mode. 4 - reserved 3 INTENA Logic 1 enables all DC interrupts. Bus reset value: unchanged;

for details, see Section 8.6.3. 2 DBGMOD Logic 1 enables debug mode, where all NAKs and errors will

generate an interrupt. Logic 0 selects normal operation, where

interrupts are generated on every ACK (bulk endpoints) or after

every data transfer (isochronous endpoints).

Bus reset value: unchanged. 1 - reserved 0 SOFTCT Logic 1 enables SoftConnect (see Section 7.5). This bit is

ignored if EXTPUL = 1 in the DcHardwareConﬁguration register

(see Table 82). Bus reset value: unchanged.

[1]

13.1.4 DcHardwareConﬁguration register (R/W: BBH/BAH)

This command is used to access the DcHardwareConﬁguration register, which consists of 2 bytes. The ﬁrst (lower) byte contains the device conﬁguration and control values, the second (upper) byte holds the clock control bits and the clock division factor. The bit allocation is given in Table 82. A bus reset will not change any of the programmed bit values.

The DcHardwareConﬁguration register controls the connection to the USB bus, clock activity and power supply during ‘suspend’ state, output clock frequency, DMA operating mode and pin conﬁgurations (polarity, signalling mode).

Code (Hex): BA/BB — write/read DcHardwareConﬁguration register Transaction — write/read 1 word

Table 82: DcHardwareConﬁguration register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol reserved EXTPUL NOLAZY CLKRUN CLKDIV[3:0] Reset 00100011 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Bit 7 6 5 4 3 2 1 0 Symbol DAKOLY DRQPOL DAKPOL EOTPOL WKUPCS PWROFF INTLVL INTPOL Reset 01000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 83: DcHardwareConﬁguration register: bit description

Bit Symbol Description

15 - reserved 14 EXTPUL Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used

on pin D+ and that SoftConnect is not used. Bus reset value:

unchanged. 13 NOLAZY Logic 1 disables output on pin CLKOUT of the LazyClock

frequency (100 kHz ± 50 %) during ‘suspend’ state. Logic 0

causes pin CLKOUT to switch to LazyClock output after

approximately 2 ms delay, following the setting of bit GOSUSP

in the DcMode register. Bus reset value: unchanged. 12 CLKRUN Logic 1 indicates that the internal clocks are always running,

even during ‘suspend’ state. Logic 0 switches off the internal

oscillator and PLL, when they are not needed. During ‘suspend’

state this bit must be made logic 0 to meet the suspend current

requirements. The clock is stopped after a delay of

approximately 2 ms, following the setting of bit GOSUSP in the

DcMode register. Bus reset value: unchanged. 11 to 8 CLKDIV[3:0] This ﬁeld speciﬁes the clock division factor N, which controls the

clock frequency on output CLKOUT. The output frequency in

MHz is given by 48 / (N + 1). The clock frequency range is

3 MHz to 48 MHz (N=0to15). with a reset value of 12 MHz

(N = 3). The hardware design guarantees no glitches during

frequency change. Bus reset value: unchanged. 7 DAKOLY Logic 1 selects DACK-only DMA mode. Logic 0 selects

8237 compatible DMA mode. Bus reset value: unchanged. 6 DRQPOL Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged. 5 DAKPOL Selects

Bus reset value: unchanged. 4 EOTPOL Selects EOT pin signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged. 3 WKUPCS Logic 1 enables remote wake-up via a LOW level on input pin

CS (V

Bus reset value: unchanged. 2 PWROFF Logic 1 enables powering-off during ‘suspend’ state. Output

D_SUSPEND pin is conﬁgured as a power switch control signal

for external devices (HIGH during ‘suspend’). This value should

always be initialized to logic 1. Bus reset value: unchanged. 1 INTLVL Selects the interrupt signalling mode on output pin INT2

(0 = level, 1 = pulsed). In pulsed mode an interrupt produces an

166 ns pulse. See Section 8.6.3 for details.

Bus reset value: unchanged. 0 INTPOL Selects INT2 pin signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged.

DACK2 pin signal polarity (0 = active LOW).

must be present for wake-up onCS).

BUS

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13.1.5 DcInterruptEnable register (R/W: C3H/C2H)

This command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). That is, if an interrupt event occurs while the interrupt is not enabled, nothing will be seen on the interrupt pin. Even if you then enable the interrupt during the interrupt event, there will still be no interrupt seen on the interrupt pin, see Figure 42.

The DcInterrupt register will not register any interrupt, if it is not already enabled using the DcInterruptEnable register. The DcInterruptEnable register is not an Interrupt Mask register.

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Full-speed USB single-chip host and device controller

DcInterruptEnable

disabled

INT2 pin

interrupt

event

occurs

Pin INT2: HIGH = de-assert; LOW= assert; INTENA = 1.

DcInterruptEnable

enabled

interrupt is cleared

interrupt

event

occurs

004aaa197

Fig 42. Interrupt pin waveform.

A bus reset will not change any of the programmed bit values. The command accesses the DcInterruptEnable register, which consists of 4 bytes.

The bit allocation is given in Table 84.

Remark: For details on interrupt control, see Section 8.6.3. Code (Hex): C2/C3 — write/read DcInterruptEnable register

Transaction — write/read 2 words

Table 84: DcInterruptEnable register: bit allocation

Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol IEP14 IEP13 IEP12 IEP11 IEP10 IEP9 IEP8 IEP7 Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Full-speed USB single-chip host and device controller

Bit 15 14 13 12 11 10 9 8 Symbol IEP6 IEP5 IEP4 IEP3 IEP2 IEP1 IEP0IN IEP0OUT Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved SP_IEEOT IEPSOF IESOF IEEOT IESUSP IERESM IERST Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 85: DcInterruptEnable register: bit description

Bit Symbol Description

31 to 24 - reserved; must write logic 0 23 to 10 IEP14 to IEP1 Logic 1 enables interrupts from the indicated endpoint. 9 IEP0IN Logic 1 enables interrupts from the control IN endpoint. 8 IEP0OUT Logic 1 enables interrupts from the control OUT endpoint. 7 - reserved 6 SP_IEEOT Logic 1 enables interrupt upon detection of a short packet. 5 IEPSOF Logic 1 enables 1 ms interrupts upon detection of Pseudo SOF. 4 IESOF Logic 1 enables interrupt upon SOF detection. 3 IEEOT Logic 1 enables interrupt upon EOT detection. 2 IESUSP Logic 1 enables interrupt upon detection of ‘suspend’ state. 1 IERESM Logic 1 enables interrupt upon detection of a ‘resume’ state. 0 IERST Logic 1 enables interrupt upon detection of a bus reset.

13.1.6 DcDMAConﬁguration register (R/W: F1H/F0H)

This command deﬁnes the DMA conﬁguration of ISP1161A’s DC and enables/disables DMA transfers. The command accesses the DcDMAConﬁguration register, which consists of 2 bytes. The bit allocation is given in Table 86. A bus reset will clear bit DMAEN (DMA disabled), all other bits remain unchanged.

Code (Hex): F0/F1 — write/read DMA Conﬁguration Transaction — write/read 1 word

Table 86: DcDMAConﬁguration register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol CNTREN SHORTP reserved reserved reserved reserved reserved reserved Reset 0

[1]

Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol EPDIX[3:0] DMAEN reserved BURSTL[1:0] Reset 0

[1]

Access R/W R/W R/W R/W R/W R/W R/W R/W

[1] Unchanged by a bus reset.

[1]

000

[1]

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Table 87: DcDMAConﬁguration register: bit description

Bit Symbol Description

15 CNTREN Logic 1 enables the generation of an EOT condition, when the

14 SHORTP Logic 1 enables short/empty packet mode. When receiving

13 to 8 - reserved 7 to 4 EPDIX[3:0] Indicates the destination endpoint for DMA, see Table 70. 3 DMAEN Writing logic 1 enables DMA transfer, logic 0 forces the end of

2 - reserved 1 to 0 BURSTL[1:0] Selects the DMA burst length:

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DcDMACounter register reaches zero. Bus reset value:

unchanged.

(OUTendpoint) a short/empty packet an EOT condition is

generated. When transmitting (IN endpoint), this bit should be

cleared. Bus reset value: unchanged.

an ongoing DMA transfer. Reading this bit indicates whether

DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit

is cleared by a bus reset.

00 — single-cycle mode (1 byte)

01 — burst mode (4 bytes)

10 — burst mode (8 bytes)

11 — burst mode (16 bytes).

Bus reset value: unchanged.

For selecting an endpoint for device DMA transfer, see Section 11.2.

13.1.7 DcDMACounter register (R/W: F3H/F2H)

This command accesses the DcDMACounter register. The bit allocation is given in

Table 88. Writing to the register sets the number of bytes for a DMA transfer.Reading

the register returns the number of remaining bytes in the current transfer.A bus reset will not change the programmed bit values.

The internal DMA counter is automatically reloaded from the DcDMACounter register when DMA is re-enabled (DMAEN = 1). See Section 13.1.6 for more details.

Code (Hex): F2/F3 — write/read DcDMACounter register Transaction — write/read 1 word

Table 88: DcDMACounter register: bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol DMACR[15:8] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol DMACR[7:0] Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W

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Table 89: DcDMACounter register: bit description

Bit Symbol Description

15 to 0 DMACR[15:0] DMA Counter register

13.1.8 Reset Device (F6H)

This command resets the ISP1161A DC in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values.

Code (Hex): F6 — reset the device Transaction — none

13.2 Data ﬂow commands

Data ﬂow commands are used to manage the data transmission between the USB endpoints and the system microprocessor. Much of the data ﬂow is initiated via an interrupt to the microprocessor. The data ﬂow commands are used to access the endpoints and determine whether the endpoint FIFOs contain valid data.

Remark: The IN bufferof an endpoint contains input data for the host, the OUT buffer receives output data from the host.

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Full-speed USB single-chip host and device controller

13.2.1 Write/Read Endpoint Buffer (R/W: 10H,12H-1FH/01H–0FH)

This command is used to access endpoint FIFO buffers for reading or writing. First, the buffer pointer is reset to the beginning of the buffer. Following the command, a maximum of (M + 1) words can be written or read, with M given by (N + 1) DIV 2, N representing the size of the endpoint buffer. After each read/write action the buffer pointer is automatically incremented by 2.

In DMA access, the ﬁrst word (the packet length) is skipped: transfers start at the second word of the endpoint buffer. When reading, the ISP1161A DC can detect the last word via the End of Packet (EOP) condition. When writing to a bulk/interrupt endpoint, the endpoint buffer must be completely ﬁlled before sending the data to the host. Exception: when a DMA transfer is stopped by an external EOT condition, the current buffer content (full or not) is sent to the host.

Remark: Reading data after a Write Endpoint Buffer command or writing data after a Read Endpoint Buffer command will cause unpredictable behavior of the ISP1161A DC.

Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14) Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14) Transaction — write/read maximum (M + 1) words (isochronous endpoint: N ≤ 1023,

bulk/interrupt endpoint: N ≤ 32) The data in the endpoint FIFO must be organized as shown in Table 90. An example

of endpoint FIFO access is given Table 91.

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Table 90: Endpoint FIFO organization

Word # Description

0 (lower byte) packet length (lower byte) 0 (upper byte) packet length (upper byte) 1 (lower byte) data byte 1 1 (upper byte) data byte 2 …… M = (N + 1) DIV 2 data byte N

Table 91: Example of endpoint FIFO access

A0 Phase Bus lines Word # Description

1 command D[7:0] - command code (00H to 1FH)

0 data D[15:0] 0 packet length 0 data D[15:0] 1 data word 1 (data byte 2, data byte 1) 0 data D[15:0] 2 data word 2 (data byte 4, data byte 3) ……………

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D[15:8] - ignored

Remark: There is no protection against writing or reading past a buffer’sboundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation. Data residing in an OUT buffer are only meaningful after a successful transaction. Exception: during DMA access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer.

13.2.2 DcEndpointStatus register (R: 50H–5FH)

This command is used to read the status of an endpoint FIFO. The command accesses the DcEndpointStatus register, the bit allocation of which is shown in

Table 92. Reading the DcEndpointStatus register will clear the interrupt bit set for the

corresponding endpoint in the DcInterrupt register (see Table 108). All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by

the Stall/Unstall commands and by the reception of a SETUP token (see

Section 13.2.3).

Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14) Transaction — read 1 word

Table 92: DcEndpointStatus register: bit allocation

Bit 7 6 5 4 3 2 1 0 Symbol EPSTAL EPFULL1 EPFULL0 DATA_PID OVER

WRITE

Reset 00000000 Access RRRRRRRR

SETUPT CPUBUF reserved

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Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features

3. Applications

4. Ordering information

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

7.1 PLL clock multiplier

7.2 Bit clock recovery

7.3 Analog transceivers

7.4 Philips Serial Interface Engine (SIE)

7.5 SoftConnect

7.6 GoodLink

8. Microprocessor bus interface

8.1 Programmed I/O (PIO) addressing mode

8.2 DMA mode

8.3 Control register access by PIO mode

8.4 FIFO buffer RAM access by PIO mode

8.5 FIFO buffer RAM access by DMA mode

8.6 Interrupts

9. USB host controller (HC)

9.1 HC’s four USB states

9.3 PTD data structure

9.4 HC internal FIFO buffer RAM structure

9.5 HC operational model

9.6 Microprocessor loading

9.7 Internal pull-down resistors for downstream ports

9.8 OC detection and power switching control

9.9 Suspend and wake-up

10. HC registers

10.1 HC control and status registers

10.2 HC frame counter registers

10.3 HC Root Hub registers

10.4 HC DMA and interrupt control registers

10.5 HC miscellaneous registers

10.6 HC buffer RAM control registers

11. USB device controller (DC)

11.1 DC data transfer operation

11.2 Device DMA transfer

11.3 Endpoint descriptions

11.4 Suspend and resume

12. DC DMA transfer

12.1 Selecting an endpoint for DMA transfer

12.2 8237 compatible mode

12.3 DACK-only mode

12.4 End-Of-Transfer conditions

13. DC commands and registers

13.1 Initialization commands