Philips IRLZ34N Datasheet

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N
Logic level TrenchMOS

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic envelope using ’trench’V
technology.Thedevicefeatures very I
low on-state resistance and has P
integral zener diodes giving ESD T
protectionupto 2kV. Itis intended for R
useinswitchedmodepowersupplies resistance VGS = 10 V
and general purpose switching
applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 gate
2 drain
3 source

TM

transistor

DS

D

tot
j

DS(ON)

Drain-source voltage 55 V
Drain current (DC) 30 A
Total power dissipation 68 W
Junction temperature 175 ˚C
Drain-source on-state 35 mΩ

tab

d

g

tab drain

123

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

Drain-source voltage Tj = 25 ˚C to 175˚C - 55 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -55V
Gate-source voltage - ± 13 V
Continuous drain current Tmb = 25 ˚C - 30 A

Tmb = 100 ˚C - 21 A

I

DM

P

D

Tj, T

Pulsed drain current Tmb = 25 ˚C - 110 A
Total power dissipation Tmb = 25 ˚C - 68 W
Operating junction and - 55 175 ˚C

stg

storage temperature

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R
R

th j-mb

th j-a

Thermal resistance junction - 2.2 K/W
to mounting base
Thermal resistance junction 60 - K/W
to ambient

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

February 1999 1 Rev 1.000

Electrostatic discharge Human body model (100 pF, 1.5 kΩ)-2kV
capacitor voltage, all pins

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N

Logic level TrenchMOS

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

(BR)GSS

V

GS(TO)

R

DS(ON)

g

fs

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V

Drain-source on-state VGS = 5 V; ID = 17 A - 28 46 mΩ
resistance VGS = 10 V; ID = 17 A - 26 35 mΩ

Forward transconductance VDS = 25 V; ID = 15 A 12 40 - S
Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA

Zero gate voltage drain VDS = 55 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Total gate charge ID = 30 A; V
Gate-source charge - 6 - nC
Gate-drain (Miller) charge - 11 - nC

Turn-on delay time VDD = 30 V; ID = 25 A; - 14 21 ns
Turn-on rise time VGS = 5 V; RG = 10 Ω - 77 110 ns
Turn-off delay time Resistive load - 55 80 ns
Turn-off fall time - 48 65 ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH

Internal source inductance Measured from source lead to source - 7.5 - nH

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1050 1400 pF
Output capacitance - 205 245 pF
Feedback capacitance - 113 150 pF

TM

transistor

(SOT78 package only)
bond pad

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3 V

Tj = 175˚C - - 74 mΩ

Tj = 175˚C - - 20 µA

= 44 V; VGS = 5 V - 22.5 - nC

DD

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

February 1999 2 Rev 1.000

Continuous source current - - 30 A
(body diode)
Pulsed source current (body - - 110 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 34 A; VGS = 0 V - 1.0 - V

Reverse recovery time IF = 34 A; -dIF/dt = 100 A/µs; - 40 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.16 - µC

Philips Semiconductors Product specification

N-channel enhancement mode IRLZ34N

Logic level TrenchMOS

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

W

DSS

Drain-source non-repetitive ID = 20 A; VDD ≤ 25 V; VGS = 5 V; - 45 mJ
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

TM

transistor

Normalised Power Derating

= f(Tmb)

D 25 ˚C

1000

ID/A

100

10

1

1 10 100

RDS(ON) = VDS/ID

DC

VDS/V

tp =
1 us

10us

100 us

1 ms
10ms

100ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

ZTH/ (K/W)

10

1

0.5

0.2

0.1

0.05

0.1

0.02

0

0.01

1.0E-06 0.0001 0.01 1 100

p

t

P

D

t/s

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

p

t

D =

T

t

T

February 1999 3 Rev 1.000