Philips IRFZ24N Datasheet

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ24N
TrenchMOS

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope using V
’trench’ technology. The device I
featuresverylowon-state resistance P
and has integral zener diodes giving T
ESD protection up to 2kV. It is R
intended for use in switched mode resistance VGS = 10 V
power supplies and general purpose
switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 gate
2 drain
3 source

TM

transistor

DS

D

tot
j

DS(ON)

Drain-source voltage 55 V
Drain current (DC) 17 A
Total power dissipation 45 W
Junction temperature 175 ˚C
Drain-source on-state 70 mΩ

tab

d

g

tab drain

123

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T

DS
DGR

tot

stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 20 V
Drain current (DC) Tmb = 25 ˚C - 17 A
Drain current (DC) Tmb = 100 ˚C - 12 A
Drain current (pulse peak value) Tmb = 25 ˚C - 68 A
Total power dissipation Tmb = 25 ˚C - 45 W
Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R
R

th j-mb

th j-a

Thermal resistance junction to - - 3.3 K/W
mounting base
Thermal resistance junction to in free air 60 - K/W
ambient

February 1999 1 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ24N

TrenchMOS

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V

(BR)GSS

R

DS(ON)

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

TM

transistor

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V

Tj = 175˚C 1.0 - - V

Tj = -55˚C - - 4.4

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 µA

Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.04 1 µA

Tj = 175˚C - - 20 µA
Gate source breakdown voltage IG = ±1 mA; 16 - - V
Drain-source on-state VGS = 10 V; ID = 10 A - 60 70 mΩ
resistance Tj = 175˚C - - 157 mΩ

Forward transconductance VDS = 25 V; ID = 10 A 1 - - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 365 500 pF

Output capacitance - 110 135 pF
Feedback capacitance - 60 85 pF

Total gate charge VDD = 44 V; ID = 20 A; VGS = 10 V - - 19 nC
Gate-cource charge - - 5.2 nC
Gate-drain (miller) charge - - 7.2 nC

Turn-on delay time VDD = 30 V; ID = 10 A; - 9 14 ns
Turn-on rise time VGS = 10 V; RG = 10 Ω - 1621ns
Turn-off delay time Resistive load - 14 25 ns
Turn-off fall time - 13 20 ns

Internal drain inductance Measured from contact screw on - 3.5 - nH

tab to centre of die

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

Internal source inductance Measured from source lead 6 mm - 7.5 - nH

from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

SD

t

rr

Q

rr

February 1999 2 Rev 1.000

Continuous reverse drain - - 17 A
current
Pulsed reverse drain current - - 68 A
Diode forward voltage IF = 19.7 A; VGS = 0 V - 0.95 1.2 V

Reverse recovery time IF = 19.7 A; -dIF/dt = 100 A/µs; - 32 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.12 - µC

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ24N

TrenchMOS

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Fig.1. Normalised power dissipation.

TM

transistor

Drain-source non-repetitive ID = 10 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

Normalised Power Derating

Tmb / C

100

ID/A

RDS(ON) = VDS/ID

10

DC

1

1 10 100

VDS/V

tp =
1 us

10us

100 us

1 ms

10ms
100ms

Fig.3. Safe operating area. Tmb = 25 ˚C

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

ID & IDM = f(VDS); IDM single pulse; parameter t

p

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 10 V

D 25 ˚C

Zth/ (K/W)

10

0.5

1

0.2

0.1

0.05

0.1

0.02
0

0.01

1.0E-06 0.0001 0.01 1 100
t/s

p

t

P

D

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

D =

p

t
T

t

February 1999 3 Rev 1.000