Philips HEF4024B User Manual
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4024B
MSI
7-stage binary counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
7-stage binary counter
DESCRIPTION
The HEF4024B is a 7-stage binary ripple counter with a
clock input (CP), and overriding asynchronous master
reset input (MR) and seven fully buffered parallel outputs
(O0to O6). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of CP. Each
counter stage is a static toggle flip-flop.
HEF4024B
MSI
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4024BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4024BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4024BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
PINNING
CP clock input (HIGH to LOW triggered)
MR master reset input
O
to O
0
6
APPLICATION INFORMATION
Some examples of applications for the HEF4024B are:
• Frequency dividers
• Time delay circuits
FAMILY DATA, I
See Family Specifications
buffered parallel outputs
LIMITS category MSI
DD
January 1995 2
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