Philips FB2031BB, CD3206BB Datasheet

INTEGRATED CIRCUITS

FB2031

9-bit latched/registered/pass-thru

Futurebus+ transceiver

Product specification

1995 May 25

IC19 Data Handbook

m n r

Philips Semiconductors	Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver	FB2031

FEATURES

•Latched, registered or straight through in either A to B or B to A path

•Drives heavily loaded backplanes with equivalent load impedances down to 10Ω.

•High drive 100mA BTL open collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces power consumption

•Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Each BTL driver has a dedicated Bus GND for a signal return

•Controlled output ramp and multiple GND pins minimize ground bounce

•Glitch-free power up/power down operation

•Low ICC current

•Tight output skew

•Supports live insertion

QUICK REFERENCE DATA

SYMBOL

PARAMETER

TYPICAL

UNIT

tPLH

Propagation delay

2.7

ns

tPHL

An to Bn

tPLH

Propagation delay

4.4

ns

tPHL

Bn to An

4.2

CO

Output capacitance

±

only)

6

pF

(B0

Bn

IOL

Output current

±

only)

100

mA

(B0

Bn

AIn to

Bn

17

mA

(outputs Low or High)

ICC

Supply current

to AOn (outputs Low)

50

mA

Bn

to AOn (outputs High)

25

Bn

ORDERING INFORMATION

	PACKAGE	COMMERCIAL RANGE	INDUSTRIAL RANGE	DRAWING
		VCC = 5V±10%; Tamb = 0°C to +70°C	VCC = 5V±10%; Tamb = ±40°C to +85°C	NUMBER
	52-pin Plastic Quad Flat Pack (QFP)	FB2031BB	CD3206BB	SOT379-1

PIN CONFIGURATION

				A1	LOGICGND	A0			V			BIASV					OEA	OEB0		OEB1		TCK(option)			V		TMS(option)					BUSGND		B0
									CC																CC
				52	51	50			49			48					47	46		45		44			43		42					41		40
																																					BUS GND
LOGIC GND	1																																	39
A2	2																																	38			B1
																																					BUS GND
LOGIC GND	3																																	37
A3	4																																		36		B2
				9-Bit latched/registered transceiver
LOGIC GND	5																																		35		BUS GND
A4													FB2031
	6																																	34			B3
																																					BUS GND
LOGIC GND	7																																		33
A5	8									52-lead PQFP																								32			B4
LOGIC GND																																					BUS GND
	9																																	31
A6
	10																																	30			B5
LOGIC GND	11																																	29			BUS GND
A7
	12																																	28			B6
LOGIC GND																																					BUS GND
	13																																	27
				14	15	16			17			18				19		20		21		22			23		24				25			26

A8

SEL1

LCBA

BGV

LCAB

BGGND

SEL0

(option)TDO

(option)TDI

V

B8

BUSGND

B7

CC

CC

SG00060

1995 May 25

2

853-1714 15279

Philips Semiconductors	Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver	FB2031

DESCRIPTION

The FB2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FB2031 is intended to provide the electrical interface to a high performance wired-OR bus.

The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A ª00º configures latches in both directions. A ª10º configures thru mode in both directions. A ª01º configures register mode in both directions. A ª11º configures register mode in the A-to-B direction and latch mode in the B-to-A direction.

When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output.

The 3-State A port is enabled by asserting a

High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled.

When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pullup voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port).

The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V.

The B-port interfaces to ªBackplane Transceiver Logicº (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.

Output clamps are provided on the BTL outputs to further reduce switching noise.

The ªV º clamp reduces inductive ringing

OH

effects during a Low-to-High transition. The

ªV º clamp is always active. The other

OH

clamp, the ªtrapped reflectionº clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition.

To support live insertion, OEB0 is held Low during power on/off cycles to insure glitchfree B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and

2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin.

The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides.

These pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS

GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a ªhardº signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot.

As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.

PACKAGE THERMAL CHARACTERISTICS

PARAMETER	CONDITION	52-PIN PLASTIC QFP
θja	Still air	80°C/W
θja	300 Linear feet per minute air flow	58°C/W
θjc	Thermally mounted on one side to heat sink	20°C/W

PIN DESCRIPTION

	SYMBOL							PIN NUMBER	TYPE	NAME AND FUNCTION
		A0 ± A8						50, 52, 2, 4, 6, 8, 10, 12, 14	I/O	BiCMOS data inputs/3-State outputs (TTL)
								40, 38, 36, 34, 32,
		B0 ± B8							I/O	Data inputs/Open Collector outputs, High current drive (BTL)
								30, 28, 26, 24
			OEB0					46	Input	Enables the B outputs when High
			OEB1					45	Input	Enables the B outputs when Low
			OEA					47	Input	Enables the A outputs when High
	BUS GND							25, 27, 29, 31, 33,	GND	Bus ground (0V)
								35, 37, 39, 41
	LOGIC GND							51, 1, 3, 5, 7, 9, 11, 13	GND	Logic ground (0V)
			VCC					23, 43, 49	Power	Positive supply voltage
		BIAS V						48	Power	Live insertion pre-bias pin
	BG VCC							17	Power	Band Gap threshold voltage reference
	BG GND							19	GND	Band Gap threshold voltage reference ground
			SEL0					20	Input	Mode select
			SEL1					15	Input	Mode select
			LCAB					18	Input	A to B clock/latch enable (transparent latch when Low)
			LCBA					16	Input	B to A clock/latch enable (transparent latch when Low)
			TMS					42	Input	Test Mode Select (optional, if not implemented then no connect)
			TCK					44	Input	Test Clock (optional, if not implemented then no connect)
			TDI					22	Input	Test Data In (optional, if not implemented then no connect)
			TDO					21	Output	Test Data Out (optional, if not implemented then shorted to TDI)

1995 May 25

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Philips Semiconductors	Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver	FB2031

FUNCTION TABLE

MODE

INPUTS

OUTPUTS

An

Bn*

OEB0

OEB1

OEA

LCAB

LCBA

SEL0

SEL1

An

Bn

An to

thru mode

L

Ð

H

L

L

X

X

H

L

input

H**

Bn

H

Ð

H

L

L

X

X

H

L

input

L

An to

transparent latch

L

Ð

H

L

L

L

X

L

L

input

H**

Bn

H

Ð

H

L

L

L

X

L

L

input

L

An to

latch and read

l

Ð

H

L

L

↑

X

L

L

input

H**

Bn

h

Ð

H

L

L

↑

X

L

L

input

L

outputs latched and read

latched

Bn

X

Ð

H

L

X

H

X

L

L

X

(preconditioned latch)

data

An to

register

l

Ð

H

L

L

↑

X

X

H

input

H**

Bn

h

Ð

H

L

L

↑

X

X

H

input

L

to An thru mode

Ð

L

Disable

H

X

X

H

L

H

input

Bn

Ð

H

Disable

H

X

X

H

L

L

input

Ð

L

Disable

H

X

L

L

L

H

input

to An transparent latch

Ð

H

Disable

H

X

L

L

L

L

input

Bn

Ð

L

Disable

H

X

L

H

H

H

input

Ð

H

Disable

H

X

L

H

H

L

input

Ð

l

Disable

H

X

↑

L

L

H

input

to An latch and read

Ð

h

Disable

H

X

↑

L

L

L

input

Bn

Ð

l

Disable

H

X

↑

H

H

H

input

Ð

h

Disable

H

X

↑

H

H

L

input

Ð

X

X

X

H

X

H

L

L

latched

X

An outputs latched and read

data

(preconditioned latch)

Ð

X

X

X

H

X

H

H

H

latched

X

data

to An register

Ð

l

Disable

H

X

↑

L

H

H

input

Bn

Ð

h

Disable

H

X

↑

L

H

L

input

Disable

outputs

X

X

L

X

X

X

X

X

X

X

H**

Bn

X

X

X

H

X

X

X

X

X

X

H**

Disable An outputs

X

X

X

X

L

X

X

X

X

Z

X

FUNCTION SELECT TABLE

		MODE SELECTED				SEL0			SEL1
		Thru mode				H			L
		Register mode (An to Bn)				X			H
		Latch mode (An to Bn)				L			L
		Register mode (Bn to An)				L			H
		Latch mode (Bn to An)				L			L
						H			H
NOTES:
H	=	High voltage level	X	=	Don't care			* =	Precaution should be taken to
							Bn
L	=	Low voltage level	Z	=	High-impedance (OFF) state		ensure B inputs do not float. If they do, they
l	=	Low voltage level one set-up time	Ð	=	Input not externally driven		are equal to Low state.
prior to the Low-to-High LCXX transition			↑	=	Low-to-High transition		Disable		= OEB0 is Low or		is High.
										OEB1
h	=	High voltage level one set-up time	H**	=	Goes to level of pull-up voltage
prior to the Low-to-High LCXX transition

1995 May 25

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Philips Semiconductors	Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver	FB2031

LOGIC DIAGRAM

OEB0	46
OEB1	45
OEA	47
		D	Q
		E
		D	Q		MUX		24 B8
	14	Clk			A B
A8
			MUX		Q	D
					Q	D
			A	B		E
		D	Q		Q	D
		E				Clk
		D	Q		MUX		26
							B7
	12	Clk			A B		28
A7
	10		MUX				30
					Q	D
	8		A	B		E	32
								BTL
TTL	6				Q	D	34
		D	Q			Clk
	4
		E					36
	2	D	Q		MUX		38 B1
		Clk			A B
	52
A1
			MUX		Q	D
			A	B		E
		D	Q		Q	D
		E				Clk
		D	Q		MUX		40
							B0
	50	Clk			A B
A0
			MUX		Q	D
			A	B		E
					Q	D
LCAB	18					Clk
SEL0	20	Decode
SEL1	15	In	Out
LCBA	16

	TMS	42	(JTAG Boundary Scan pins)		LOGIC GND	= 1, 3, 5, 7, 9, 11, 13, 51
		44
	TCK				BUS GND	= 25, 27, 29, 31, 33, 35, 37, 39, 41
		22			BIAS V	=	48
	TDI
	TDO	21			VCC	=	23, 43, 49
					BG VCC	=	17
					BG GND	=	19	SG00061

1995 May 25

5

Philips Semiconductors	Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver	FB2031

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device.

Unless otherwise noted these limits are over the operating free-air temperature range.

SYMBOL

PARAMETER

RATING

UNIT

VCC

Supply voltage

-0.5 to +7.0

V

VIN

Input voltage

All inputs except

±

-1.2 to +7.0

V

B0

B8

±

-1.2 to +3.5

B0

B8

IIN

Input current

-40 to +5.0

mA

VOUT

Voltage applied to output in High output state

-0.5 to +VCC

V

IOUT

Current applied to output in Low output state

A0 ± A8

48

mA

±

200

B0

B8

TSTG

Storage temperature

-65 to +150

°C

RECOMMENDED OPERATING CONDITIONS (Industrial)

SYMBOL

PARAMETER

LIMITS

UNIT

MIN

TYP

MAX

VCC

Supply voltage

4.5

5.0

5.5

V

VIH

High-level input voltage

Except

2.0

V

B0±B8

±

1.62

1.55

B0

B8

VIL

Low-level input voltage

Except

±

0.8

V

B0

B8

±

1.47

B0

B8

IIK

Input clamp current

Control inputs

-40

mA

±

& A0 ± A8

-18

B0

B8

IOH

High-level output current

A0

± A8

-3

mA

IOL

Low-level output current

A0

± A8

24

mA

±

100

B0

B8

IIA

Off device input current

Except

±

100

μA

B0

B8,

VI = 0 to 5.5V, VCC = 0V

COB

Output capacitance of B port

6

7

pF

Tamb

Operating free-air temperature range

±40

+85

°C

RECOMMENDED OPERATING CONDITIONS (Commercial)

SYMBOL

PARAMETER

LIMITS

UNIT

MIN

TYP

MAX

VCC

Supply voltage

4.5

5.0

5.5

V

VIH

High-level input voltage

Except

2.0

V

B0±B8

±

1.62

1.55

B0

B8

VIL

Low-level input voltage

Except

±

0.8

V

B0

B8

±

1.47

B0

B8

IIK

Input clamp current

Control inputs

-40

mA

±

& A0 ± A8

-18

B0

B8

IOH

High-level output current

A0

± A8

-3

mA

IOL

Low-level output current

A0

± A8

24

mA

±

100

B0

B8

IIA

Off device input current

Except

±

100

μA

B0

B8,

VI = 0 to 5.5V, VCC = 0V

COB

Output capacitance of B port

6

7

pF

Tamb

Operating free-air temperature range

0

+70

°C

1995 May 25

6