INTEGRATED CIRCUITS
FB2031
9-bit latched/registered/pass-thru
Futurebus+ transceiver
Product specification |
1995 May 25 |
IC19 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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9-bit latched/registered/pass-thru Futurebus+ transceiver |
FB2031 |
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•Latched, registered or straight through in either A to B or B to A path
•Drives heavily loaded backplanes with equivalent load impedances down to 10Ω.
•High drive 100mA BTL open collector drivers on B-port
•Allows incident wave switching in heavily loaded backplane buses
•Reduced BTL voltage swing produces less noise and reduces power consumption
•Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity
•Compatible with IEEE Futurebus+ or proprietary BTL backplanes
•Each BTL driver has a dedicated Bus GND for a signal return
•Controlled output ramp and multiple GND pins minimize ground bounce
•Glitch-free power up/power down operation
•Low ICC current
•Tight output skew
•Supports live insertion
SYMBOL |
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PARAMETER |
TYPICAL |
UNIT |
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tPLH |
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Propagation delay |
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2.7 |
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tPHL |
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An to Bn |
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tPLH |
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Propagation delay |
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4.4 |
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tPHL |
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Bn to An |
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4.2 |
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CO |
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Output capacitance |
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only) |
6 |
pF |
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(B0 |
Bn |
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IOL |
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Output current |
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only) |
100 |
mA |
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(B0 |
Bn |
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AIn to |
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Bn |
17 |
mA |
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(outputs Low or High) |
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ICC |
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Supply current |
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to AOn (outputs Low) |
50 |
mA |
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Bn |
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to AOn (outputs High) |
25 |
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Bn |
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PACKAGE |
COMMERCIAL RANGE |
INDUSTRIAL RANGE |
DRAWING |
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VCC = 5V±10%; Tamb = 0°C to +70°C |
VCC = 5V±10%; Tamb = ±40°C to +85°C |
NUMBER |
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52-pin Plastic Quad Flat Pack (QFP) |
FB2031BB |
CD3206BB |
SOT379-1 |
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A1 |
LOGICGND |
A0 |
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V |
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BIASV |
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OEA |
OEB0 |
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OEB1 |
TCK(option) |
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V |
TMS(option) |
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BUSGND |
B0 |
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CC |
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CC |
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52 |
51 |
50 |
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49 |
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48 |
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47 |
46 |
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45 |
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44 |
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43 |
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42 |
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41 |
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40 |
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BUS GND |
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LOGIC GND |
1 |
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39 |
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A2 |
2 |
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38 |
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B1 |
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BUS GND |
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LOGIC GND |
3 |
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37 |
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A3 |
4 |
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36 |
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B2 |
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9-Bit latched/registered transceiver |
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LOGIC GND |
5 |
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35 |
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BUS GND |
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A4 |
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FB2031 |
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6 |
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34 |
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B3 |
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BUS GND |
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LOGIC GND |
7 |
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33 |
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A5 |
8 |
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52-lead PQFP |
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32 |
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B4 |
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LOGIC GND |
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BUS GND |
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9 |
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31 |
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A6 |
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30 |
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B5 |
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LOGIC GND |
11 |
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29 |
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BUS GND |
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A7 |
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28 |
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B6 |
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LOGIC GND |
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BUS GND |
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13 |
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27 |
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14 |
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16 |
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17 |
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18 |
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19 |
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22 |
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23 |
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24 |
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25 |
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26 |
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A8 |
SEL1 |
LCBA |
BGV |
LCAB |
BGGND |
SEL0 |
(option)TDO |
(option)TDI |
V |
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B8 |
BUSGND |
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B7 |
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CC |
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CC |
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SG00060
1995 May 25 |
2 |
853-1714 15279 |
Philips Semiconductors |
Product specification |
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9-bit latched/registered/pass-thru Futurebus+ transceiver |
FB2031 |
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The FB2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FB2031 is intended to provide the electrical interface to a high performance wired-OR bus.
The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A ª00º configures latches in both directions. A ª10º configures thru mode in both directions. A ª01º configures register mode in both directions. A ª11º configures register mode in the A-to-B direction and latch mode in the B-to-A direction.
When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output.
The 3-State A port is enabled by asserting a
High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled.
When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pullup voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port).
The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to ªBackplane Transceiver Logicº (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.
Output clamps are provided on the BTL outputs to further reduce switching noise.
The ªV º clamp reduces inductive ringing
OH
effects during a Low-to-High transition. The
ªV º clamp is always active. The other
OH
clamp, the ªtrapped reflectionº clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off cycles to insure glitchfree B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin.
The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides.
These pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS
GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a ªhardº signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot.
As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.
PARAMETER |
CONDITION |
52-PIN PLASTIC QFP |
θja |
Still air |
80°C/W |
θja |
300 Linear feet per minute air flow |
58°C/W |
θjc |
Thermally mounted on one side to heat sink |
20°C/W |
SYMBOL |
PIN NUMBER |
TYPE |
NAME AND FUNCTION |
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A0 ± A8 |
50, 52, 2, 4, 6, 8, 10, 12, 14 |
I/O |
BiCMOS data inputs/3-State outputs (TTL) |
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40, 38, 36, 34, 32, |
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B0 ± B8 |
I/O |
Data inputs/Open Collector outputs, High current drive (BTL) |
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30, 28, 26, 24 |
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OEB0 |
46 |
Input |
Enables the B outputs when High |
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OEB1 |
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45 |
Input |
Enables the B outputs when Low |
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OEA |
47 |
Input |
Enables the A outputs when High |
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BUS GND |
25, 27, 29, 31, 33, |
GND |
Bus ground (0V) |
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35, 37, 39, 41 |
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LOGIC GND |
51, 1, 3, 5, 7, 9, 11, 13 |
GND |
Logic ground (0V) |
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VCC |
23, 43, 49 |
Power |
Positive supply voltage |
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BIAS V |
48 |
Power |
Live insertion pre-bias pin |
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BG VCC |
17 |
Power |
Band Gap threshold voltage reference |
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BG GND |
19 |
GND |
Band Gap threshold voltage reference ground |
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SEL0 |
20 |
Input |
Mode select |
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SEL1 |
15 |
Input |
Mode select |
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LCAB |
18 |
Input |
A to B clock/latch enable (transparent latch when Low) |
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LCBA |
16 |
Input |
B to A clock/latch enable (transparent latch when Low) |
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TMS |
42 |
Input |
Test Mode Select (optional, if not implemented then no connect) |
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TCK |
44 |
Input |
Test Clock (optional, if not implemented then no connect) |
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TDI |
22 |
Input |
Test Data In (optional, if not implemented then no connect) |
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TDO |
21 |
Output |
Test Data Out (optional, if not implemented then shorted to TDI) |
1995 May 25 |
3 |
Philips Semiconductors |
Product specification |
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9-bit latched/registered/pass-thru Futurebus+ transceiver |
FB2031 |
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MODE |
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INPUTS |
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OUTPUTS |
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An |
Bn* |
OEB0 |
OEB1 |
OEA |
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LCAB |
LCBA |
SEL0 |
SEL1 |
An |
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Bn |
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An to |
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thru mode |
L |
Ð |
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H |
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L |
L |
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X |
X |
H |
L |
input |
H** |
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Bn |
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H |
Ð |
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H |
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L |
L |
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X |
X |
H |
L |
input |
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L |
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An to |
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transparent latch |
L |
Ð |
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H |
|
L |
L |
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L |
X |
L |
L |
input |
H** |
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Bn |
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H |
Ð |
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H |
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L |
L |
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L |
X |
L |
L |
input |
|
L |
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An to |
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latch and read |
l |
Ð |
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H |
|
L |
L |
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↑ |
X |
L |
L |
input |
H** |
|||||||
Bn |
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h |
Ð |
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H |
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L |
L |
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↑ |
X |
L |
L |
input |
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L |
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outputs latched and read |
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latched |
||||||
Bn |
X |
Ð |
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H |
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L |
X |
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H |
X |
L |
L |
X |
|||||||||||
(preconditioned latch) |
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data |
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An to |
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register |
l |
Ð |
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H |
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L |
L |
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↑ |
X |
X |
H |
input |
H** |
|||||||
Bn |
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h |
Ð |
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H |
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L |
L |
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↑ |
X |
X |
H |
input |
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L |
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to An thru mode |
Ð |
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L |
Disable |
H |
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X |
X |
H |
L |
H |
input |
||||||||||
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Bn |
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Ð |
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H |
Disable |
H |
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X |
X |
H |
L |
L |
input |
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Ð |
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L |
Disable |
H |
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X |
L |
L |
L |
H |
input |
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to An transparent latch |
Ð |
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H |
Disable |
H |
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X |
L |
L |
L |
L |
input |
||||||||||
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Bn |
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Ð |
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L |
Disable |
H |
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X |
L |
H |
H |
H |
input |
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Ð |
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H |
Disable |
H |
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X |
L |
H |
H |
L |
input |
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Ð |
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l |
Disable |
H |
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X |
↑ |
L |
L |
H |
input |
||||||
|
|
to An latch and read |
Ð |
|
h |
Disable |
H |
|
X |
↑ |
L |
L |
L |
input |
||||||||||
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Bn |
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Ð |
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l |
Disable |
H |
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X |
↑ |
H |
H |
H |
input |
||||||||||||
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Ð |
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h |
Disable |
H |
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X |
↑ |
H |
H |
L |
input |
||||||
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Ð |
|
X |
X |
|
X |
H |
|
X |
H |
L |
L |
latched |
|
X |
|||
An outputs latched and read |
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data |
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|||||||||||||||||||
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||||||||
(preconditioned latch) |
Ð |
|
X |
X |
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X |
H |
|
X |
H |
H |
H |
latched |
|
X |
|||||||||
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data |
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to An register |
Ð |
|
l |
Disable |
H |
|
X |
↑ |
L |
H |
H |
input |
||||||||||
|
Bn |
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|||||
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Ð |
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h |
Disable |
H |
|
X |
↑ |
L |
H |
L |
input |
||||||||||||
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||||
Disable |
|
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outputs |
X |
|
X |
L |
|
X |
X |
|
X |
X |
X |
X |
X |
H** |
|||||||
Bn |
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||||||
X |
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X |
X |
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H |
X |
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X |
X |
X |
X |
X |
H** |
|||||||||||
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|||||||||
Disable An outputs |
X |
|
X |
X |
|
X |
L |
|
X |
X |
X |
X |
Z |
|
X |
|||||||||
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MODE SELECTED |
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SEL0 |
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SEL1 |
||
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Thru mode |
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H |
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L |
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Register mode (An to Bn) |
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X |
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H |
||
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Latch mode (An to Bn) |
|
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L |
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L |
||
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Register mode (Bn to An) |
|
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L |
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H |
||
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Latch mode (Bn to An) |
|
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L |
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L |
||
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H |
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H |
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NOTES: |
|
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|
H |
= |
High voltage level |
X |
= |
Don't care |
|
* = |
Precaution should be taken to |
|||
Bn |
|||||||||||
L |
= |
Low voltage level |
Z |
= |
High-impedance (OFF) state |
ensure B inputs do not float. If they do, they |
|||||
l |
= |
Low voltage level one set-up time |
Ð |
= |
Input not externally driven |
are equal to Low state. |
|||||
prior to the Low-to-High LCXX transition |
↑ |
= |
Low-to-High transition |
Disable |
= OEB0 is Low or |
|
is High. |
||||
OEB1 |
|||||||||||
h |
= |
High voltage level one set-up time |
H** |
= |
Goes to level of pull-up voltage |
|
|
|
|
|
|
prior to the Low-to-High LCXX transition |
|
|
|
|
|
|
|
|
|
1995 May 25 |
4 |
Philips Semiconductors |
Product specification |
|
|
|
|
9-bit latched/registered/pass-thru Futurebus+ transceiver |
FB2031 |
|
|
|
|
OEB0 |
46 |
|
|
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OEB1 |
45 |
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OEA |
47 |
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D |
Q |
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E |
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D |
Q |
|
MUX |
|
24 B8 |
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||
|
14 |
Clk |
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A B |
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A8 |
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MUX |
Q |
D |
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Q |
D |
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A |
B |
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E |
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D |
Q |
|
Q |
D |
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||
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E |
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Clk |
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D |
Q |
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MUX |
|
26 |
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B7 |
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12 |
Clk |
|
|
A B |
|
28 |
|
A7 |
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||
|
10 |
|
MUX |
|
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30 |
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Q |
D |
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||
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||
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8 |
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A |
B |
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E |
32 |
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BTL |
|||
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TTL |
6 |
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Q |
D |
34 |
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|||
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D |
Q |
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Clk |
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4 |
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E |
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36 |
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||
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2 |
D |
Q |
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MUX |
|
38 B1 |
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||||
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Clk |
|
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A B |
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52 |
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A1 |
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MUX |
Q |
D |
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||
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A |
B |
|
E |
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D |
Q |
|
Q |
D |
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||
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E |
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Clk |
|
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D |
Q |
|
MUX |
|
40 |
|
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|
B0 |
|
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|
50 |
Clk |
|
|
A B |
|
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|
A0 |
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||
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||
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MUX |
Q |
D |
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A |
B |
|
E |
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Q |
D |
|
|
LCAB |
18 |
|
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|
Clk |
|
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|
SEL0 |
20 |
Decode |
|
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|
|||
SEL1 |
15 |
In |
Out |
|
|
|
|
|
LCBA |
16 |
|
|
|
|
|
|
|
|
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|
|
TMS |
42 |
(JTAG Boundary Scan pins) |
LOGIC GND |
= 1, 3, 5, 7, 9, 11, 13, 51 |
|
|||
44 |
|
|||||||
TCK |
BUS GND |
= 25, 27, 29, 31, 33, 35, 37, 39, 41 |
||||||
|
||||||||
22 |
|
|
BIAS V |
= |
48 |
|
||
TDI |
|
|
|
|||||
TDO |
21 |
|
|
VCC |
= |
23, 43, 49 |
|
|
|
|
|
|
BG VCC |
= |
17 |
|
|
|
|
|
|
BG GND |
= |
19 |
SG00061 |
|
|
|
|
|
|
|
|
1995 May 25 |
5 |
Philips Semiconductors |
Product specification |
|
|
|
|
9-bit latched/registered/pass-thru Futurebus+ transceiver |
FB2031 |
|
|
|
|
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL |
PARAMETER |
|
|
|
|
|
|
|
|
|
|
RATING |
UNIT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC |
Supply voltage |
|
|
|
|
|
|
|
|
|
|
-0.5 to +7.0 |
V |
VIN |
Input voltage |
|
All inputs except |
|
± |
|
|
-1.2 to +7.0 |
V |
||||
B0 |
B8 |
||||||||||||
|
|
|
|
± |
|
|
-1.2 to +3.5 |
|
|||||
|
|
|
B0 |
B8 |
|
||||||||
IIN |
Input current |
|
|
|
|
|
|
|
|
|
|
-40 to +5.0 |
mA |
VOUT |
Voltage applied to output in High output state |
|
|
|
|
|
|
|
|
|
|
-0.5 to +VCC |
V |
IOUT |
Current applied to output in Low output state |
|
A0 ± A8 |
48 |
mA |
||||||||
|
|
|
|
|
± |
|
|
200 |
|
||||
|
|
|
B0 |
B8 |
|
||||||||
TSTG |
Storage temperature |
|
|
|
|
|
|
|
|
|
|
-65 to +150 |
°C |
SYMBOL |
PARAMETER |
|
|
|
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|
|
LIMITS |
|
UNIT |
|
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|
MIN |
TYP |
MAX |
|
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|
|
VCC |
Supply voltage |
|
|
|
|
|
|
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|
|
|
|
4.5 |
5.0 |
5.5 |
V |
VIH |
High-level input voltage |
|
Except |
|
|
|
|
|
|
|
2.0 |
|
|
V |
||||
B0±B8 |
|
|
||||||||||||||||
|
|
|
|
|
± |
|
|
|
|
|
|
1.62 |
1.55 |
|
|
|||
|
|
|
B0 |
B8 |
|
|
||||||||||||
VIL |
Low-level input voltage |
|
Except |
|
|
|
± |
|
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0.8 |
V |
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B0 |
B8 |
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± |
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1.47 |
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B0 |
B8 |
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IIK |
Input clamp current |
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Control inputs |
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-40 |
mA |
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± |
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& A0 ± A8 |
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-18 |
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B0 |
B8 |
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IOH |
High-level output current |
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A0 |
± A8 |
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-3 |
mA |
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IOL |
Low-level output current |
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A0 |
± A8 |
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24 |
mA |
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± |
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100 |
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B0 |
B8 |
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IIA |
Off device input current |
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Except |
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± |
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100 |
μA |
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B0 |
B8, |
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VI = 0 to 5.5V, VCC = 0V |
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COB |
Output capacitance of B port |
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6 |
7 |
pF |
Tamb |
Operating free-air temperature range |
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±40 |
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+85 |
°C |
SYMBOL |
PARAMETER |
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LIMITS |
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UNIT |
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MIN |
TYP |
MAX |
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VCC |
Supply voltage |
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4.5 |
5.0 |
5.5 |
V |
VIH |
High-level input voltage |
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Except |
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2.0 |
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V |
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B0±B8 |
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± |
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1.62 |
1.55 |
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B0 |
B8 |
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VIL |
Low-level input voltage |
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Except |
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± |
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0.8 |
V |
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B0 |
B8 |
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± |
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1.47 |
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|||||
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B0 |
B8 |
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|||||||||||
IIK |
Input clamp current |
|
Control inputs |
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|
-40 |
mA |
|||||||||||
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± |
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& A0 ± A8 |
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|
-18 |
|
|||||
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B0 |
B8 |
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|||||||||||
IOH |
High-level output current |
|
A0 |
± A8 |
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|
-3 |
mA |
||||||||||
IOL |
Low-level output current |
|
A0 |
± A8 |
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|
24 |
mA |
||||||||||
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± |
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|
100 |
|
|||||
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B0 |
B8 |
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|
|||||||||||
IIA |
Off device input current |
|
Except |
|
± |
|
|
|
|
100 |
μA |
|||||||
|
B0 |
B8, |
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|
||||||||||||||
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VI = 0 to 5.5V, VCC = 0V |
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COB |
Output capacitance of B port |
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|
6 |
7 |
pF |
Tamb |
Operating free-air temperature range |
|
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0 |
|
+70 |
°C |
1995 May 25 |
6 |