Philips Semiconductors Product specification
Silicon Diffused Power Transistor BU1706AB
GENERAL DESCRIPTION
High-voltage, high-speed switching npn transistor in a plastic envelope suitable for surface mounting, intended for
use in high frequency electronic lighting ballast applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
V
CESM
V
CEO
I
C
I
CM
P
tot
V
CEsat
I
Csat
t
f
PINNING - SOT404 PIN CONFIGURATION SYMBOL
Collector-emitter voltage peak value VBE = 0 V - 1750 V
Collector-emitter voltage (open base) - 850 V
Collector current (DC) - 5 A
Collector current peak value - 8 A
Total power dissipation Tmb ≤ 25 ˚C - 100 W
Collector-emitter saturation voltage IC = 1.5 A; IB = 0.3 A - 1.0 V
Collector saturation current 1.5 - A
Fall time ICM = 1.5 A; I
= 0.3 A 0.25 0.6 µs
B(on)
PIN DESCRIPTION
mb
c
1 base
2 collector
b
3 emitter
mb collector
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
I
C
I
CM
I
B
I
BM
-I
-I
P
T
T
CESM
CEO
B(AV)
BM
tot
stg
j
Collector-emitter voltage peak value VBE = 0 V - 1750 V
Collector-emitter voltage (open base) - 850 V
Collector current (DC) - 5 A
Collector current peak value - 8 A
Base current (DC) - 3 A
Base current peak value - 5 A
Reverse base current average over any 20ms period - 100 mA
Reverse base current peak value - 4 A
Total power dissipation Tmb ≤ 25 ˚C - 100 W
Storage temperature -65 150 ˚C
Junction temperature - 150 ˚C
THERMAL RESISTANCES
2
13
e
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
R
th j-mb
th j-a
Thermal resistance junction to mounting - 1.25 K/W
base
Thermal resistance junction to ambient minimum footprint, FR4 board 55 - K/W
February 1998 1 Rev 1.000
Philips Semiconductors Product specification
Silicon Diffused Power Transistor BU1706AB
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
CES
I
CES
I
CES
I
EBO
V
CEOsust
V
CEsat
V
BEsat
h
FE
h
FE
h
FE
Collector cut-off current
Emitter cut-off current VEB = 12 V; IC = 0 A - - 1 mA
Collector-emitter sustaining voltage IB = 0 A; IC = 100 mA; 750 - - V
Collector-emitter saturation voltage IC = 1.5 A; IB = 0.3 A - - 1.0 V
Base-emitter saturation voltage IC = 1.5 A; IB = 0.3 A - - 1.3 V
DC current gain IC = 5 mA; VCE = 10 V 8 - -
DYNAMIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Switching times (resistive load) I
t
on
t
s
t
f
t
s
t
f
t
s
t
f
Turn-on time 1.1 1.5 µs
Turn-off storage time 5 6.5 µs
Turn-off fall time 0.75 1.0 µs
Switching times (inductive load) I
Turn-off storage time 2.0 3.0 µs
Turn-off fall time 0.25 0.6 µs
Switching times (inductive load) I
Turn-off storage time 2.2 3.3 µs
Turn-off fall time 0.2 0.7 µs
1
VBE = 0 V; VCE = V
VBE = 0 V; VCE = 1500 V - - 20 µA
VBE = 0 V; VCE = V
CESMmax
; - - 2.0 mA
CESMmax
- - 1.0 mA
Tj = 125 ˚C
L = 25 mH
IC = 400 mA; VCE = 3 V 12 18 35
IC = 1.5 A; VCE = 1 V 5 7 -
= 1.5 A; I
Con
= 1.5 A; I
Con
= -I
Bon
Bon
= 0.3 A
Boff
= 0.3 A; LB = 1 µH;
-VBB = 5 V
= 1.5 A; I
Con
-VBB = 5 V; Tj = 100 ˚C
= 0.3 A; LB = 1 µH;
Bon
IC / mA
250
200
100
0
VCE / V
min
VCEOsust
CEOsust
.
100-200R
Horizontal
Oscilloscope
Vertical
300R
30-60 Hz
6V
Fig.1. Test circuit for V
1 Measured with half sine-wave voltage (curve tracer).
1R
CEOsust
+ 50v
. Fig.2. Oscilloscope display for V
February 1998 2 Rev 1.000
Philips Semiconductors Product specification
Silicon Diffused Power Transistor BU1706AB
VCC
R
L
VIM
0
R
B
T.U.T.
tp
T
Fig.3. Test circuit resistive load. VIM = -6 to +8 V
VCC = 250 V; tp = 20 µs; δ = tp / T = 0.01.
RB and RL calculated from I
90 %
IC
ton
IB
10 %
tr 30ns
Con
and I
ts
toff
requirements.
Bon
ICon
90 %
10 %
tf
IBon
VCC
LC
VCL
IBon
-VBB
LB
T.U.T.
Fig.6. Test Circuit RBSOA.
VCC = 150 V; -VBB = 5 V; LC = 2 mH; VCL ≤ 1500 V;
LB = 1 µH
ICon
90 %
IC
10 %
ts
toff
IB
IBon
tf
t
t
-IBoff
Fig.4. Switching times waveforms with resistive load.
VCC
LC
IBon
-VBB
LB
T.U.T.
Fig.5. Test circuit inductive load.
VCC = 300 V; -VBE = 5 V; LB = 1 uH
Fig.7. Switching times waveforms with inductive load.
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Normalised Power Derating
Tmb / C
Fig.8. Normalised power dissipation.
PD% = 100⋅PD/PD
25 ˚C
-IBoff
= f (Tmb)
February 1998 3 Rev 1.000