Philips BF1202WR, BF1202R, BF1202 Datasheet
DISCRETE SEMICONDUCTORS
DATA SH EET
BF1202; BF1202R; BF1202WR
N-channel dual-gate PoLo
MOS-FETs
Product specification
Supersedes data of 1999 Dec 01
2000 Mar 29
Philips Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs
FEATURES
• Short channel transistor with high
forwardtransferadmittancetoinput
capacitance ratio
• Low noise gain controlled amplifier
• Partly internal self-biasing circuit to
ensure good cross-modulation
performanceduring AGC andgood
DC stabilization.
APPLICATIONS
• VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.
DESCRIPTION
PINNING
PIN DESCRIPTION
1 source
2 drain
3 gate 2
4 gate 1
handbook, 2 columns
BF1202; BF1202R;
BF1202WR
handbook, 2 columns
Top view
BF1202R marking code: LEp
Fig.2 Simplified outline
(SOT143R).
34
page
43
12
MSB035
43
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
12
Top view
MSB014
21
Top view
MSB842
protect against excessive input
voltage surges. The BF1202,
BF1202 marking code: LDp
BF1202WR marking code: LE
BF1202R and BF1202WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
Fig.1 Simplified outline
(SOT143B).
Fig.3 Simplified outline
(SOT343R).
packages respectively.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DS
I
D
P
tot
y
forward transfer admittance 25 30 40 mS
fs
C
ig1-ss
C
rss
drain-source voltage −−10 V
drain current −−30 mA
total power dissipation −−200 mW
input capacitance at gate 1 − 1.7 2.2 pF
reverse transfer capacitance f = 1 MHz − 15 30 fF
F noise figure f = 800 MHz − 1.1 1.8 dB
X
mod
cross-modulation input level for k = 1% at
100 105 − dBµV
40 dB AGC
T
j
operating junction temperature −−150 °C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
2000 Mar 29 2
Philips Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. Tsis the temperature of the soldering point of the source lead.
THERMAL CHARACTERISTICS
drain-source voltage − 10 V
drain current − 30 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation
BF1202; BF1202R T
BF1202WR T
≤ 113 °C; note 1 − 200 mW
s
≤ 119 °C; note 1 − 200 mW
s
storage temperature −65 +150 °C
operating junction temperature − 150 °C
SYMBOL PARAMETER VALUE UNIT
R
th j-s
thermal resistance from junction to soldering point
BF1202; BF1202R 185 K/W
BF1202WR 155 K/W
150
MCD951
Ts (°C)
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
050
(1)
(2)
100 200
(1) BF1202WR.
(2) BF1202; BF1202R.
Fig.4 Power derating curve.
2000 Mar 29 3
Philips Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
STATIC CHARACTERISTICS
Tj=25°C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
(BR)DSS
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-SS
I
G2-SS
Note
1. R
connects G1to VGG=5V.
G1
drain-source breakdown voltage V
gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
forward source-gate 1 voltage V
forward source-gate 2 voltage V
gate 1-source threshold voltage V
gate 2-source threshold voltage V
drain-source current V
gate 1 cut-off current V
gate 2 cut-off current V
G1-S=VG2-S
G2-S=VDS
G1-S=VDS
G2-S=VDS
G1-S=VDS
=4V; VDS=5V; ID= 100 µA 0.3 1.0 V
G2-S
=5V; VDS=5V; ID= 100 µA 0.3 1.2 V
G1-S
=4V; VDS=5V; RG1= 120 kΩ;
G2-S
note 1
G2-S=VDS
G1-S=VDS
= 0; ID=10µA10−V
= 0; I
= 0; I
= 0; I
= 0; I
=10mA 6 − V
G1-S
=10mA 6 − V
G2-S
= 10 mA 0.5 1.5 V
S-G1
= 10 mA 0.5 1.5 V
S-G2
816mA
= 0; V
= 0; V
=5V − 50 nA
G1-S
=4V − 20 nA
G2-S
DYNAMIC CHARACTERISTICS
Common source; T
=25°C; V
amb
=4V; VDS=5V; ID= 12 mA; unless otherwise specified.
G2-S
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
y
forward transfer admittance pulsed; Tj=25°C 253040mS
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F noise figure f = 10.7 MHz; G
G
tr
X
mod
input capacitance at gate 1 f = 1 MHz − 1.7 2.2 pF
input capacitance at gate 2 f = 1 MHz − 1 − pF
output capacitance f = 1 MHz − 0.85 − pF
reverse transfer capacitance f = 1 MHz − 15 30 fF
= 20 mS; BS=0 − 911dB
S
f = 400 MHz; Y
f = 800 MHz; Y
S=YS opt
S=YS opt
power gain f = 200 MHz; GS= 2 mS; BS=B
GL= 0.5 mS; BL=B
f = 400 MHz; G
GL= 1 mS; BL=B
f = 800 MHz; G
GL= 1 mS; BL=B
L opt
= 2 mS; BS=B
S
L opt
= 3.3 mS; BS=B
S
L opt
S opt
S opt
S opt
− 0.9 1.5 dB
− 1.1 1.8 dB
;
− 34.5 − dB
;
− 30.5 − dB
;
− 26.5 − dB
cross-modulation input level for k = 1%; fw= 50 MHz;
f
= 60 MHz; note 1
unw
at 0 dB AGC 90 −−dBµV
at 10 dB AGC − 92 − dBµV
at 40 dB AGC 100 105 − dBµV
Note
1. Measured in Fig.21 test circuit.
2000 Mar 29 4
Philips Semiconductors Product specification
N-channel dual-gate PoLo MOS-FETs
2 V
1.5 V
1 V
V
G1-S
MCD952
2.5 V
(V)
20
handbook, halfpage
I
D
(mA)
16
12
8
4
0
02
V
= 4 V
G2-S
3.5 V
3 V
0.4 0.8 1.2 1.6
24
handbook, halfpage
I
D
(mA)
16
8
0
010
BF1202; BF1202R;
BF1202WR
MCD953
V
= 1.5 V
G1-S
1.4 V
1.3 V
1.2 V
1.1 V
1 V
0.9 V
2
648
VDS (V)
VDS=5V.
Tj=25°C.
Fig.5 Transfer characteristics; typical values.
100
handbook, halfpage
I
G1
(µA)
80
60
40
20
0
0 2.5
0.5 1 1.5 2
V
G2-S
= 4 V
3.5 V
V
3 V
2.5 V
2 V
1.5 V
1 V
G1-S
MCD954
(V)
V
=4V.
G2-S
Tj=25°C.
Fig.6 Output characteristics; typical values.
40
handbook, halfpage
y
fs
(mS)
30
20
10
0
0
420
V
= 4 V
G2-S
81216
MCD955
3.5 V
3 V
2.5 V
2 V
ID (mA)
VDS=5V.
VDS=5V.
Tj=25°C.
Tj=25°C.
Fig.7 Gate 1 current as a function of gate 1
voltage; typical values.
2000 Mar 29 5
VDS=5V.
Tj=25°C.
Fig.8 Forward transfer admittance as a function
of drain current; typical values.
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