Philips BF1201WR, BF1201R, BF1201 Datasheet

DISCRETE SEMICONDUCTORS

DATA SHEET

BF1201; BF1201R; BF1201WR

N-channel dual-gate PoLo
MOS-FETs

Preliminary specification 1999 Nov 26

Philips Semiconductors Preliminary specification

N-channel dual-gate PoLo MOS-FETs

FEATURES

• Short channel transistor with high

forward transfer admittance to input
capacitance ratio

• Low noise gain controlled amplifier

• Partly internal self-biasing circuit to

ensure good cross-modulation
performance during AGC and good
DC stabilization.

APPLICATIONS

• VHF and UHF applications with

3 - 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.

DESCRIPTION

PINNING

PIN DESCRIPTION

1 source
2drain
3 gate 2
4 gate 1

handbook, 2 columns

BF1201; BF1201R;

BF1201WR

handbook, 2 columns

Top view MSB035

BF1201R marking code: LBp

Fig.2 Simplified outline

(SOT143R).

34

book, halfpage

43

12

43

Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source

12

Top view MSB014

21

Top view MSB842

protect against excessive input
voltage surges. The BF1201,

BF1201 marking code: LAp

BF1201WR marking code: LA

BF1201R and BF1201WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic

Fig.1 Simplified outline

(SOT143B).

Fig.3 Simplified outline

(SOT343R).

packages respectively.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

y

 forward transfer admittance 23 28 35 mS

fs

C

ig1-ss

C

rss

drain-source voltage −−10 V
drain current −−30 mA
total power dissipation −−200 mW

input capacitance at gate 1 − 2.6 3.1 pF
reverse transfer capacitance f = 1 MHz − 15 30 fF

F noise figure f = 400 MHz − 11.8dB
X

mod

cross-modulation input level for k = 1% at

105 −−dBµV

40 dB AGC

T

j

operating junction temperature −−150 °C

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.

1999 Nov 26 2

Philips Semiconductors Preliminary specification

Fig.4 Power derating curve.

N-channel dual-gate PoLo MOS-FETs

BF1201; BF1201R;

BF1201WR

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. T

s

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-s

drain-source voltage − 10 V
drain current − 30 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation Ts≤ 110 °C; note 1 200 mW
storage temperature −65 +150 °C
operating junction temperature − +150 °C

is the temperature of the soldering point of the source lead.

thermal resistance from junction to soldering point 200 K/W

250

P

tot

(mW)

200

150

100

50

0

0 50 100 150 200

T

(°C)

s

1999 Nov 26 3