Philips 80c652, 83c652 DATASHEETS

INTEGRATED CIRCUITS

80C652/83C652

CMOS single-chip 8-bit microcontrollers

Product specification
Supersedes data of 1996 Aug 15
IC20 Data Handbook

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1997 Dec 05

Phlips Semiconductors Product specification

80C652/83C652CMOS single-chip 8-bit microcontrollers

DESCRIPTION

The P80C652/83C652 Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
80C652/83C652 has the same instruction set
as the 80C51. Three versions of the
derivative exist:

83C652 — 8k bytes mask programmable

80C652 — ROMless version
87C652 — EPROM version (described in a

This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 8XC652 contains a non-volatile
8k × 8 read-only program memory, a volatile
256 × 8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), a
multi-source, two-priority-level, nested
interrupt structure, an I
and on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC652 can be expanded using standard
TTL compatible memories and logic.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16(24)MHz crystal, 58% of
the instructions are executed in 0.75(0.5)µs
and 40% in 1.5(1)µs. Multiply and divide
instructions require 3(2)µs.

ROM

separate chapter)

2

C interface, UART

FEATURES

•80C51 central processing unit

•8k × 8 ROM expandable externally to

64k bytes

•256 × 8 RAM, expandable externally to

64k bytes

•Two standard 16-bit timer/counters

•Four 8-bit I/O ports

2

•I

C-bus serial I/O port with byte oriented

master and slave functions

•Full-duplex UART facilities

•Power control modes

– Idle mode
– Power-down mode

•ROM code protection

•Extended frequency range: 3.5 to 24 MHz

•Three operating ambient temperature

ranges:

0 to +70°C
–40 to +85°C
–40 to +125°C

PIN CONFIGURATIONS

P1.0

1

P1.1

2

P1.2

3

P1.3

4

P1.4

5

P1.5

6

SCL/P1.6

SDA/P1.7

INT0
INT1

RST
RxD/P3.0
TxD/P3.1

/P3.2

/P3.3
T0/P3.4
T1/P3.5

WR

/P3.6

/P3.7

RD

XTAL2
XTAL1

V

SS

7

7

8

PLASTIC

9

DUAL

IN-LINE

10

PACKAGE

11
12
13

14
15
16
17
18
19
20

6140

40
39
38
37
36
35
34
33
32
31

30
29
28
27
26

25
24
23
22

21

V

DD

P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7

EA

ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13

P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8

39

LOGIC SYMBOL

1997 Dec 05

RST

XTAL1
XTAL2

PSEN

ALE

FUNCTIONS

ALTERNATE

INT0
INT1

EA

PORT 3

RxD

TxD

T0
T1

WR

RD

DD

PLASTIC

LEADED

CHIP

VSSV

PORT 0PORT 1PORT 2

DATA BUS

ADDRESS AND

SCL
SDA

ADDRESS BUS

17

1

11

CARRIER

18 28

44

PLASTIC

QUAD

FLAT

PACK

12 22

29

34

33

23

2

Phlips Semiconductors Product specification

80C652/83C652CMOS single-chip 8-bit microcontrollers

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS

6140

7

PLASTIC

LEADED CHIP

CARRIER

17

18 28

Pin Function Pin Function

1 NC* 23 NC*
2 P1.0 24 P2.0/A8
3 P1.1 25 P2.1/A9
4 P1.2 26 P2.2/A10
5 P1.3 27 P2.3/A11
6 P1.4 28 P2.4/A12
7 P1.5 29 P2.5/A13
8 P1.6/SCL 30 P2.6/A14

9 P1.7/SDA 31 P2.7/A15
10 RST 32 PSEN
11 P3.0/RxD 33 ALE
12 NC* 34 NC*
13 P3.1/TxD 35 EA
14 P3.2/INT0 36 P0.7/AD7
15 P3.3/INT1 37 P0.6/AD6
16 P3.4/T0 38 P0.5/AD5
17 P3.5/T1 39 P0.4/AD4
18 P3.6/WR 40 P0.3/AD3
19 P3.7/RD 41 P0.2/AD2
20 XTAL2 42 P0.1/AD1
21 XTAL1 43 P0.0/AD0
22 V

SS

*DO NOT CONNECT

44 V

39

29

DD

PLASTIC QUAD FLAT PACK PIN FUNCTIONS

44 34

1

PLASTIC

QUAD

FLAT

PACK

11

12 22

Pin Function Pin Function

1 P1.5 23 P2.5/A13
2 P1.6/SCL 24 P2.6/A14
3 P1.7/SDA 25 P2.7/A15
4 RST 26 PSEN
5 P3.0/RxD 27 ALE
6 V

SS4

7 P3.1/TxD 29
8 P3.2/INT0 30 P0.7/AD7

9 P3.3/INT1 31 P0.6/AD6
10 P3.4/T0 32 P0.5/AD5
11 P3.5/T1 33 P0.4/AD4
12 P3.6/WR 34 P0.3/AD3
13 P3.7/RD 35 P0.2/AD2
14 XTAL2 36 P0.1/AD1
15 XTAL1 37 P0.0/AD0
16 V

SS1

17 NC* 39 V
18 P2.0/A8 40 P1.0
19 P2.1/A9 41 P1.1
20 P2.2/A10 42 P1.2
21 P2.3/A11 43 P1.3
22 P2.4/A12 44 P1.4

*DO NOT CONNECT

NOTES TO QFP ONLY:

1. Due to EMC improvements, all V
(6, 16, 28, 39) must be connected to V
on the 80C652/83C652.

28 V

38 V

EA

SS2

/V

DD
SS3

SS

33

23

PP

pins

SS

1997 Dec 05

3

Phlips Semiconductors Product specification

( )

1,2

80C652/83C652CMOS single-chip 8-bit microcontrollers

ORDER INFORMATION

PHILIPS

PART ORDER NUMBER

PART MARKING

ROMless ROM

P80C652EBP P83C652EBP/xxx SOT129-1 P80C652EBPN P83C652EBPN S87C652-4N40

P80C652EBA P83C652EBA/xxx SOT187-2 P80C652EBAA P83C652EBAA S87C652-4A44

P80C652EBB P83C652EBB/xxx SOT307-2 P80C652EBBB P83C652EBBB S87C652-4B44

P80C652EFP P83C652EFP/xxx SOT129-1 P80C652EFPN P83C652EFPN S87C652-5N40

P80C652EFA P83C652EFA/xxx SOT187-2 P80C652EFAA P83C652EFAA S87C652-5A44

P80C652EFB P83C652EFB/xxx SOT307-2 P80C652EFBB P83C652EFBB S87C652-5B44

P80C652EHP P83C652EHP/xxx SOT129-1 P80C652EHPN P83C652EHPN

P80C652EHA P83C652EHA/xxx SOT187-2 P80C652EHAA P83C652EHAA

P80C652EHB P83C652EHB/xxx SOT307-2 P80C652EHBB P83C652EHBB

P80C652IBP P83C652IBP/xxx SOT129-1 P80C652IBPN P83C652IBPN

P80C652IBA P83C652IBA/xxx SOT187-2 P80C652IBAA P83C652IBAA

P80C652IBB P83C652IBB/xxx SOT307-2 P80C652IBBB P83C652IBBB

P80C652IFP P83C652IFP/xxx SOT129-1 P80C652IFPN P83C652IFPN

P80C652IFA P83C652IFA/xxx SOT187-2 P80C652IFAA P83C652IFAA

P80C652IFB P83C652IFB/xxx SOT307-2 P80C652IFBB P83C652IFBB

NOTES:

1. 80C652 and 83C652 frequency range is 3.5MHz–16MHz or 3.5MHz–24MHz.

2. For specification of the EPROM version, see the 87C652 data sheet.

3. xxx denotes the ROM code number.

3

Drawing

Number

PHILIPS NORTH AMERICA

PART ORDER NUMBER

ROMless ROM EPROM

TEMPERATURE RANGE

2

Plastic Dual In-line Package

Plastic Leaded Chip Carrier

Plastic Quad Flat Pack

Plastic Dual In-line Package

Plastic Leaded Chip Carrier

Plastic Quad Flat Pack

Plastic Dual In-line Package

Plastic Leaded Chip Carrier

Plastic Quad Flat Pack

Plastic Dual In-line Package

Plastic Leaded Chip Carrier

Plastic Quad Flat Pack

Plastic Dual In-line Package

Plastic Leaded Chip Carrier

Plastic Quad Flat Pack

(°C)

AND PACKAGE

0 to +70,

0 to +70,

0 to +70,

–40 to +85,

–40 to +85,

–40 to +85,

–40 to +125,

–40 to +125,

–40 to +125,

0 to +70,

0 to +70,

0 to +70,

–40 to +85,

–40 to +85,

–40 to +85,

FREQ

MHz

16

16

16

16

16

16

16

16

16

24

24

24

24

24

24

1997 Dec 05

4

Phlips Semiconductors Product specification

80C652/83C652CMOS single-chip 8-bit microcontrollers

BLOCK DIAGRAM

FREQUENCY
REFERENCE

COUNTERS

XTAL2 XTAL1

OSCILLATOR

INT0

EXTERNAL

INTERRUPTS

AND

TIMING

CPU

INTERNAL

INTERRUPTS

INT1

PROGRAM

MEMORY

(8K x 8 ROM)

64K BYTE BUS

EXPANSION

CONTRTOL

CONTROL

DATA

MEMORY

(256 x 8 RAM)

PROGRAMMABLE I/O

PARALLEL PORTS,

ADDRESS/DATA BUS

AND I/O PINS

T0 T1

TWO 16-BIT

TIMER/EVENT

COUNTERS

PROG SERIAL PORT
FULL DUPLEX UART

SYNCHRONOUS SHIFT

SERIAL IN SERIAL OUT

SHARED WITH

PORT 3

2

I

C SERIAL I/O

SDA

SCL

SHARED

WITH

PORT 1

1997 Dec 05

5

Phlips Semiconductors Product specification

80C652/83C652CMOS single-chip 8-bit microcontrollers

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC DIP PLCC QFP TYPE NAME AND FUNCTION

V

SS

V

DD

P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

P1.0–P1.7 1–8 2–9 40–44,

P1.6 7 8 2 I/O SCL: I2C-bus serial port clock line.
P1.7 8 9 3 I/O SDA: I2C-bus serial port data line.

P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

P3.0–P3.7 10–17 11,

RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

ALE 30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an

PSEN 29 32 26 O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It

EA 31 35 29 I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out

XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V

20 22 6, 16,

28, 39

I Ground: 0V reference. With the QFP package all VSS pins (V

connected.

SS1

to V

) must be

SS4

40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down

operation.

them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7

1–3

which are open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:

). Alternate functions include:

I

IL

written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
address byte during fetches from external program memory and during accesses to

). Port 2 emits the high-order

IL

external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

13–195,7–13

written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
the 80C51 family , as listed below:

). Port 3 also serves the special features of

IL

10 11 5 I RxD (P3.0): Serial input port
11 13 7 O TxD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt
13 15 9 I INT1 (P3.3): External interrupt
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe

device. An internal diffused resistor to V
capacitor to V

DD

.

permits a power-on reset using only an external

SS

access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency . Note that one ALE pulse is skipped during each access to external
data memory.

is activated twice each machine cycle during fetches from the external program memory.
When executing out of external program memory two activations of PSEN
during each access to external data memory. PSEN
no fetches from external program memory. PSEN

is not activated (remains HIGH) during

can sink/source 8 LSTTL inputs and can

are skipped

drive CMOS inputs without external pull–ups.

of the internal program memory ROM provided the Program Counter is less than 8192. If
during a RESET, EA
memory. EA

is held a TTL LOW level, the CPU executes out of external program

is not allowed to float.

circuits.

+ 0.5V or VSS – 0.5V, respectively.

DD

1997 Dec 05

6

Phlips Semiconductors Product specification

80C652/83C652CMOS single-chip 8-bit microcontrollers

Table 1. 8XC652/654 Special Function Registers

SYMBOL DESCRIPTION

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR:

DPH
DPL

IE*# Interrupt enable A8H EA ES1 ES0 ET1 EX1 ET0 EX0 0x000000B

IP*# Interrupt priority B8H – PS1 PS0 PT1 PX1 PT0 PX0 xx000000B

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

P1*# Port 1 90H SDA SCL FFH

P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH

P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH
PCON Power control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B

S0CON*# Serial 0 port control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H
S0BUF# Serial 0 data buffer 99H xxxxxxxxB

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00H
S1DAT# Serial 1 data DAH 00H
SP Stack pointer 81H 07H
S1ADR# Serial 1 address DBH

Data pointer
(2 bytes)
Data pointer high
Data pointer low

DIRECT

ADDRESS

83H
82H

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB

AF AE AD AC AB AA A9 A8

BF BE BD BC BB BA B9 B8

87 86 85 84 83 82 81 80

97 96 95 94 93 92 91 90

A7 A6 A5 A4 A3 A2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

9F 9E 9D 9C 9B 9A 99 98

D7 D6 D5 D4 D3 D2 D1 D0

 SLAVE ADDRESS 

GC 00H

RESET
VALUE

00H
00H

S1STA# Serial 1 status D9H SC4 SC3 SC2 SC1 SC0 0 0 0 F8H

DF DE DD DC DB DA D9 D8

S1CON*# Serial 1 control D8H CR2 ENS1 STA STO SI AA CR1 CR0 00000000B

8F 8E 8D 8C 8B 8A 89 88
TCON* Timer control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
TH1 Timer high 1 8DH 00H
TH0 Timer high 0 8CH 00H
TL1 Timer low 1 8BH 00H
TL0 Timer low 0 8AH 00H
TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.

1997 Dec 05

7