Philips 74LV107PW, 74LV107N, 74LV107DB, 74LV107D Datasheet
INTEGRATED CIRCUITS
74LV107
Dual JK flip-flop with reset;
negative-edge trigger
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Apr 20
Philips Semiconductors Product specification
74L V107Dual JK flip-flop with reset; negative-edge trigger
FEA TURES
•Wide operating: 1.0 to 5.5 V
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
CC
CC
CC
= 3.3 V,
= 3.3 V,
•Output capability: standard
•I
category: flip-flops
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr = t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
nCP to nQ
nCP to nQ
nR to nQ, nQ
f
max
C
C
I
PD
Maximum clock frequency 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop VI = GND to V
NOTE:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD × V
P
D
f
= input frequency in MHz; CL = output load capacitance in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
× V
L
2
× fi (CL × V
CC
2
× fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
2
fo) where:
CC
= 3.6 V
CL = 15 pF;
VCC = 3.3 V
DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT107.
The 74LV107 is a dual negative-edge triggered JK-type flip-flop
featuring individual J, K, clock (nCP
complementary Q and Q
outputs.
The J and K inputs must be stable one set-up time prior to the
HIGH-to-LOW clock transition for predictable operation.
The reset (nR
) is an asynchronous active LOW input. When LOW, it
overrides the clock and data inputs, forcing the Q output LOW and
the Q
output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
1
CC
) and reset (nR) inputs; also
15
15
ns
15
30 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
14-Pin Plastic DIL –40°C to +125°C 74LV107 N 74LV107 N SOT27-1
14-Pin Plastic SO –40°C to +125°C 74LV107 D 74LV107 D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +125°C 74LV107 DB 74LV107 DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV107 PW 74LV107PW DH SOT402-1
PIN CONFIGURATION
1J
1
1Q
2
1Q
3
1K
4
2Q
5
2Q
6
GND
7
14
13
12
11
10
9
8
SV00497
V
CC
1R
1CP
2K
2R
2CP
2J
PIN DESCRIPTION
PIN
NUMBER
1, 8, 4, 11 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2
2, 6 1Q, 2Q Complement flip-flop outputs
3, 5 1Q, 2Q True flip-flop outputs
7 GND Ground (0 V)
12, 9 1CP, 2CP
13, 10 1R, 2R
14 V
SYMBOL FUNCTION
Clock input
(HIGH-to-LOW, edge-triggered)
Asynchronous reset inputs
(active LOW)
CC
Positive supply voltage
1998 Apr 20 853–1904 19255
2
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
LOGIC SYMBOL
11J
82J
12 1CP
9
41K
11 2K
J
CP
2CP
K
FUNCTIONAL DIAGRAM
1
1J
J
1291CP
4
13
CP
1K
K
1R
SV00498
1Q
1Q
31Q
52Q
21Q
62Q
3
2
Q
FF
Q
R
2R
1R
10
13
Q
FF1
Q
R
LOGIC SYMBOL (IEEE/IEC)
74LV107
1
12
4
13
8
9
11
10
1J
C1
1K
1R
2J
C1
2K
2R
3
2
5
6
SV00499
8
2CP
11
10
LOGIC DIAGRAM
2J
J
Q
FF2
CP
2K
K
2R
K
J
R
CP
Q
R
2Q
2Q
SV00500
5
6
C
C
C
C
C
C
C
C
Q
C
C
Q
SV00501
1998 Apr 20
3
Philips Semiconductors Product specification
OPERATING MODES
Dual JK flip-flop with reset; negative-edge trigger
74LV107
FUNCTION TABLE
INPUTS OUTPUTS
nR nCP nJ nK nQ nQ
Asynchronous reset L X X X L H
Toggle H ↓ h h q q
Load “0” (reset) H ↓ l h L H
Load “1” (set) H ↓ h l H L
Hold “no change” H ↓ l l q q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition.
X = don’t care
↓ = HIGH-to-LOW CP transition
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
I
IK
I
OK
I
O
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
PARAMETER CONDITIONS RATING UNIT
1, 2
–0.5V < VO < VCC + 0.5V
25
mA
I
I
P
T
GND
stg
TOT
DC VCC or GND current for types with
,
– standard outputs 50
CC
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mA
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 1.0 3.3 5.5 V
CC
V
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times except for
f
Schmitt-trigger inputs
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
–40
–40
–
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
50
°C
ns/V
V
V
1998 Apr 20
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