Philips 74HCT646U, 74HCT646N, 74HCT646DB, 74HC646U, 74HC646N3 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT646

Octal bus transceiver/register; 3-state

Product specification			September 1993
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Octal bus transceiver/register; 3-state	74HC/HCT646

FEATURES

·Independent register for A and B buses

·Multiplexed real-time and stored data

·Output capability: bus driver

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT646 consist of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the “A” or “B” bus will be

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

clocked into the registers as the appropriate clock (CPAB and CPBA) goes to a HIGH logic level. Output

enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the “A” or “B” register, or in both. The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The direction (DIR) input determines which bus will receive data when OE is active

(LOW). In the isolation mode (OE = HIGH), “A” data may be stored in the “B” register and/or “B” data may be stored in the “A” register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.

The “646” is functionally identical to the “648”, but has non-inverting data paths.

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL		UNIT
				HC	HCT
	tPHL/ tPLH	propagation delay An, Bn to Bn, An	CL = 15 pF; VCC = 5 V	11	13	ns
	fmax	maximum clock frequency		69	85	MHz
	CI	input capacitance		3.5	3.5	pF
	CPD	power dissipation capacitance per channel	notes 1 and 2	30	33	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

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Philips Semiconductors					Product specification
Octal bus transceiver/register; 3-state					74HC/HCT646
PIN DESCRIPTION
PIN NO.	SYMBOL			NAME AND FUNCTION
1	CPAB			A to B clock input (LOW-to-HIGH, edge-triggered)
2	SAB			select A to B source input
3	DIR			direction control input
4, 5, 6, 7, 8, 9, 10, 11		A0 to A7		A data inputs/outputs
12	GND			ground (0 V)
20, 19, 18, 17, 16, 15, 14, 13		B0 to B7		B data inputs/outputs
21				output enable input (active LOW)
		OE
22	SBA			select B to A source input
23	CPBA			B to A clock input (LOW-to-HIGH, edge-triggered)
24	VCC			positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

September 1993

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Philips Semiconductors	Product specification
Octal bus transceiver/register; 3-state	74HC/HCT646

Fig.4 Functional diagram.

FUNCTION TABLE

				INPUTS (1)					DATA I/O (2)		FUNCTION
	OE		DIR	CPAB	CPBA	SAB	SBA	A0 to A7		B0 to B7
H			X	H or L	H or L	X	X	input		input	isolation
H			X	−	−	X	X				store A and B data
L			L	X	X	X	L	output		input	real-time B data to A bus
L			L	X	H or L	X	H				stored B data to A bus
L			H	X	X	L	X	input		output	real-time A data to B bus
L			H	H or L	X	H	X				stored A data to B bus

Notes

1.H = HIGH voltage level L = LOW voltage level

X = don’t care

− = LOW-to-HIGH level transition

2.The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs.

September 1993

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