Philips 74HCT4515U, 74HCT4515N3, 74HCT4515N, 74HCT4515D, 74HC4515U Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4515

4-to-16 line decoder/demultiplexer with input latches; inverting

Product specification			September 1993
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

4-to-16 line decoder/demultiplexer with

74HC/HCT4515

input latches; inverting

FEATURES

·Inverting outputs

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT4515 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0 to A3) with latches, a latch enable input

(LE), and an active LOW enable input (E). The 16 inverting outputs (Q0 to Q15) are mutually exclusive active LOW. When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches and the outputs remain stable.

When E is LOW, the selected output, determined by the contents of the latch, is LOW. When E is HIGH, all outputs are HIGH. The enable input (E) does not affect the state of the latch.

When the “4515” is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs.

SYMBOL	PARAMETER			CONDITIONS		TYPICAL		UNIT
					HC		HCT
tPHL/ tPLH	propagation delay An to		n	CL = 15 pF; VCC = 5 V	25		26	ns
		Q
CI	input capacitance				3.5		3.5	pF
CPD	power dissipation capacitance per package			notes 1 and 2	44		46	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi +å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

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Philips Semiconductors Product specification

4-to-16 line decoder/demultiplexer with							74HC/HCT4515
input latches; inverting
PIN DESCRIPTION
PIN NO.		SYMBOL					NAME AND FUNCTION
1		LE					latch enable input (active HIGH)
2, 3, 21, 22		A0 to A3					address inputs
11, 9, 10, 8, 7, 6, 5, 4,18, 17, 20, 19, 14, 13, 16, 15						15	multiplexer outputs (active LOW)
		Q		0 to	Q
12		GND					ground (0 V)
23							enable input (active LOW)
		E
24		VCC					positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

September 1993

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