Philips 74HCT4353N, 74HCT4353D, 74HCT4353U, 74HC4353U, 74HC4353D Datasheet

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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4353

Triple 2-channel analog multiplexer/demultiplexer with latch

Product specification

 

December 1990

File under Integrated Circuits, IC06

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Philips Semiconductors

Product specification

 

 

 

 

Triple 2-channel analog

74HC/HCT4353

multiplexer/demultiplexer with latch

FEATURES

·Wide analog input voltage range: ± 5 V

·Low “ON” resistance:

80 W (typ.) at VCC - VEE = 4.5 V 70 W (typ.) at VCC - VEE = 6.0 V 60 W (typ.) at VCC - VEE = 9.0 V

·Logic level translation:

to enable 5 V logic to communicate with ± 5 V analog signals

·Typical “break before make” built in

·Address latches provided

·Output capability: non-standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4353 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT4353 are triple 2-channel analog multiplexers/demultiplexers with two common enable inputs (E1 and E2) and a latch enable input (LE). Each

QUICK REFERENCE DATA

VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

multiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and select inputs (S1 to S3).

Each multiplexer/demultiplexer contains two bidirectional analog switches, each with one side connected to an independent input/output (nY0 and nY1) and the other side connected to a common input/output (nZ).

With E1 LOW and E2 HIGH, one of the two switches is selected (low impedance ON-state) by S1 to S3.

The data at the select inputs may be latched by using the active LOW latch enable input (LE). When LE is HIGH, the latch is transparent. When either of the two enable inputs, E1 (active LOW) and E2 (active HIGH), is inactive, all analog switches are turned off.

VCC and GND are the supply voltage pins for the digital

control inputs (S1 to S3, LE, E1 and E2). The VCC to GND ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.

The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

 

 

HC

HCT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPZH/ tPZL

turn “ON” time

 

 

1, E2 or Sn to Vos

CL = 50 pF; RL = 1 kW;

29

21

ns

E

tPHZ/ tPLZ

turn “OFF” time

 

 

 

1, E2 or Sn to Vos

VCC = 5 V

20

22

ns

 

E

CI

input capacitance

 

3.5

3.5

pF

CPD

power dissipation capacitance per switch

notes 1 and 2

23

23

pF

CS

max. switch capacitance

 

 

 

 

 

independent (Y)

 

5

5

pF

 

common (Z)

 

 

 

 

 

8

8

pF

 

 

 

 

 

 

 

 

 

 

Notes

1.CPD is used to determine the dynamic power dissipation (PD in mW):

PD =

CPD ´ VCC2 ´ fi + å {(CL + CS) ´ VCC2 ´ fo} where: fi = input frequency in MHz

CL = output load capacitance in pF fo = output frequency in MHz

CS = max. switch capacitance in pF

å {(CL ´CS) ´ VCC2 ´ fo} = sum of outputs

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

2

Philips Semiconductors

Product specification

 

 

Triple 2-channel analog

74HC/HCT4353

multiplexer/demultiplexer with latch

PIN DESCRIPTION

PIN NO.

 

SYMBOL

NAME AND FUNCTION

 

 

 

 

2, 1

 

2Y0, 2Y1

independent inputs/outputs

5

 

3Z

common input/output

6, 4

 

3Y0, 3Y1

independent inputs/outputs

3, 14

 

n.c.

not connected

7

 

 

 

enable input (active LOW)

 

E

1

 

8

 

E2

enable input (active HIGH)

9

 

VEE

negative supply voltage

10

 

GND

ground (0 V)

11

 

 

latch enable input (active LOW)

 

LE

 

15, 13, 12

 

S1 to S3

select inputs

16, 17

 

1Y0, 1Y1

independent inputs/outputs

18

 

1Z

common input/output

19

 

2Z

common input/output

20

 

VCC

positive supply voltage

Fig.1 Pin configuration.

 

Fig.2 Logic symbol.

 

Fig.3 IEC logic symbol.

 

 

 

 

 

December 1990

3

Philips 74HCT4353N, 74HCT4353D, 74HCT4353U, 74HC4353U, 74HC4353D Datasheet

Philips Semiconductors

Product specification

 

 

Triple 2-channel analog

74HC/HCT4353

multiplexer/demultiplexer with latch

FUNCTION TABLE

 

 

 

INPUTS

 

CHANNEL

 

 

 

 

 

 

 

 

E1

E2

 

LE

Sn

ON

 

 

 

H

H

 

X

X

none

 

X

L

 

X

X

none

 

L

H

 

H

L

nY0 nZ

 

L

H

 

H

H

nY1 nZ

 

L

H

 

L

X

(1)

 

X

X

 

X

(2)

 

 

 

 

 

 

 

 

 

Notes

1.Last selected channel “ON”.

2.Selected channels latched.

H = HIGH voltage level L = LOW voltage level

X = don’t care

= HIGH-to-LOW LE transition

APPLICATIONS

Analog multiplexing and demultiplexing

Digital multiplexing and demultiplexing

Signal gating

Fig.4 Functional diagram.

Fig.5 Schematic diagram (one switch).

December 1990

4

Philips Semiconductors

Product specification

 

 

Triple 2-channel analog

74HC/HCT4353

multiplexer/demultiplexer with latch

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Voltages are referenced to VEE = GND (ground = 0 V)

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

 

 

 

 

 

 

VCC

DC supply voltage

0.5

+11.0

V

 

±IIK

DC digital input diode current

 

20

mA

for VI < −0.5 V or VI > VCC + 0.5 V

±ISK

DC switch diode current

 

20

mA

for VS < −0.5 V or VS > VCC + 0.5 V

±IS

DC switch current

 

25

mA

for 0.5 V < VS < VCC + 0.5 V

±IEE

DC VEE current

 

20

mA

 

±ICC;

DC VCC or GND current

 

50

mA

 

±IGND

 

 

 

 

 

Tstg

storage temperature range

65

+150

°C

 

Ptot

power dissipation per package

 

 

 

for temperature range: 40 to +125 °C

 

 

 

 

 

74HC/HCT

 

plastic DIL

 

750

mW

above +70 °C: derate linearly with 12 mW/K

 

 

 

 

 

 

 

plastic mini-pack (SO)

 

500

mW

above +70 °C: derate linearly with 8 mW/K

 

 

 

 

 

 

PS

power dissipation per switch

 

100

mW

 

Note to ratings

1.To avoid drawing VCC current out of terminals nZ, when switch current flows in terminals nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals nZ, no VCC current will flow out of terminals nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

 

74HC

 

 

74HCT

 

UNIT

CONDITIONS

 

 

 

 

 

 

 

 

 

min.

typ.

max.

min.

typ.

max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

DC supply voltage VCCGND

2.0

5.0

 

10.0

4.5

 

5.0

 

5.5

V

see Figs 6 and 7

VCC

DC supply voltage VCCVEE

2.0

5.0

 

10.0

2.0

 

5.0

 

10.0

V

see Figs 6 and 7

VI

DC input voltage range

GND

 

 

VCC

GND

 

 

 

VCC

V

 

VS

DC switch voltage range

VEE

 

 

VCC

VEE

 

 

 

VCC

V

 

Tamb

operating ambient temperature range

40

 

 

+85

40

 

 

 

+85

°C

see DC and AC

Tamb

operating ambient temperature range

40

 

 

+125

40

 

 

 

+125

°C

CHARACTER-

 

 

 

 

 

 

 

 

 

 

 

 

ISTICS

 

 

 

 

 

 

 

 

 

 

 

 

 

tr, tf

input rise and fall times

 

 

 

1000

 

 

 

 

 

 

VCC = 2.0 V

 

 

 

6.0

 

500

 

 

6.0

 

500

ns

VCC = 4.5 V

 

 

 

 

400

 

 

 

VCC = 6.0 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250

 

 

 

 

 

 

VCC = 10.0 V

December 1990

5

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