Philips 74HCT4060U, 74HCT4060DB, 74HCT4060D, 74HC4060DB, 74HC4060D Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4060
14-stage binary ripple counter with oscillator
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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14-stage binary ripple counter with oscillator |
74HC/HCT4060 |
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FEATURES
·All active components on chip
·RC or crystal oscillator configuration
·Output capability: standard (except for RTC and CTC)
·ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4060 are high-speed Si-gate CMOS devices and are pin compatible with “4060” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT4060 are 14-stage ripple-carry counter/dividers and oscillators with three oscillator
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR).
The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case keep the other oscillator pins (RTC and CTC) floating.
The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of other input conditions.
In the HCT version, the MR input is TTL compatible, but the RS input has CMOS input switching levels and can be driven by a TTL output by using a pull-up resistor to VCC.
SYMBOL |
PARAMETER |
CONDITIONS |
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TYPICAL |
UNIT |
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HC |
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HCT |
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tPHL/ tPLH |
propagation delay |
CL = 15 pF; VCC = 5 V |
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RS to Q3 |
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31 |
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31 |
ns |
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Qn to Qn+1 |
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6 |
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6 |
ns |
tPHL |
MR to Qn |
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17 |
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18 |
ns |
fmax |
maximum clock frequency |
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87 |
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88 |
MHz |
CI |
input capacitance |
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3.5 |
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3.5 |
pF |
CPD |
power dissipation capacitance per package |
notes 1, 2 and 3 |
40 |
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40 |
pF |
Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
3. For formula on dynamic power dissipation see next pages.
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors |
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Product specification |
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14-stage binary ripple counter with oscillator |
74HC/HCT4060 |
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PIN DESCRIPTION |
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PIN NO. |
SYMBOL |
NAME AND FUNCTION |
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1, 2, 3 |
Q11 to Q13 |
counter outputs |
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7, 5, 4, 6, 14, 13, 15 |
Q3 to Q9 |
counter outputs |
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8 |
GND |
ground (0 V) |
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9 |
CTC |
external capacitor connection |
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10 |
RTC |
external resistor connection |
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11 |
RS |
clock input/oscillator pin |
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12 |
MR |
master reset |
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16 |
VCC |
positive supply voltage |
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Fig.1 Pin configuration. |
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Fig.2 Logic symbol. |
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Fig.3 IEC logic symbol. |
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December 1990 |
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Philips Semiconductors |
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Product specification |
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14-stage binary ripple counter with oscillator |
74HC/HCT4060 |
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DYNAMIC POWER DISSIPATION FOR 74HC |
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PARAMETER |
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VCC (V) |
TYPICAL FORMULA FOR PD (mW) (note 1) |
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total dynamic power |
2.0 |
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CPD ´ fosc ´ VCC2 + å (CL ´ VCC2 ´ fo) + 2Ct ´ VCC2 ´ fosc + 60 ´ VCC |
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dissipation when using the |
4.5 |
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CPD ´ fosc ´ VCC2 + å (CL ´ VCC2 ´ fo) + 2Ct ´ VCC2 ´ fosc + 1 750 ´ VCC |
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on-chip oscillator (PD) |
6.0 |
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CPD ´ fosc ´ VCC2 + å (CL ´ VCC2 ´ fo) + 2Ct ´ VCC2 ´ fosc + 3 800 ´ VCC |
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Note |
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1. GND = 0 V; Tamb = 25 °C |
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DYNAMIC POWER DISSIPATION FOR 74HCT |
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PARAMETER |
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VCC (V) |
TYPICAL FORMULA FOR PD (mW) (note 1) |
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total dynamic power |
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dissipation when using the |
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4.5 |
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CPD ´ fosc ´ VCC2 + å (CL ´ VCC2 ´ fo) + 2Ct ´ VCC2 ´ fosc + 1 750 ´ VCC |
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on-chip oscillator (PD) |
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Notes |
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1. GND = 0 V; Tamb = 25 °C |
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2. Where: fo |
= output frequency in MHz |
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fosc = oscillator frequency in MHz |
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å (CL ´ VCC2 ´ fo) = sum of outputs |
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CL |
= output load capacitance in pF |
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Ct |
= timing capacitance in pF |
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VCC = supply voltage in V
Fig.4 Functional diagram.
APPLICATIONS
·Control counters
·Timers
·Frequency dividers
·Time-delay circuits
December 1990 |
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