Philips 74HCT4052D, 74HCT4052U, 74HCT4052N, 74HCT4052DB, 74HC4052U Datasheet

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DATA SH EET
Product specification File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT4052
Dual 4-channel analog multiplexer/demultiplexer
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Dual 4-channel analog multiplexer/demultiplexer
74HC/HCT4052
FEATURES
Wide analog input voltage range: ±5 V.
Low “ON” resistance:
80 (typ.) at VCC− VEE= 4.5 V 70 (typ.) at VCC− VEE= 6.0 V 60 (typ.) at VCC− VEE= 9.0 V
Logic level translation: to enable 5 V logic to communicate with ± 5 V analog signals
Typical “break before make” built in
Output capability: non-standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4052 are high-speed Si-gate CMOS devices and are pin compatible with the “4052” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT4052 are dual 4-channel analog multiplexers/demultiplexers with common select logic. Each multiplexer has four independent inputs/outputs (nY
0
to nY3) and a common input/output (nZ). The common channel select logics include two digital select inputs (S
0
and S1) and an active LOW enable input (E). With E LOW, one of the four switches is selected (low
impedance ON-state) by S0 and S1. With E HIGH, all switches are in the high impedance OFF-state, independent of S0 and S1.
VCC and GND are the supply voltage pins for the digital control inputs (S0 and S1, and E). The VCC to GND ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The analog inputs/outputs (nY0 to nY3, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC− VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).
QUICK REFERENCE DATA
VEE= GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi +{(CL + CS) × V
CC
2
× fo)} where: fi= input frequency in MHz fo= output frequency in MHz {(CL +CS) × V
CC
2
× fo)} = sum of outputs CL= output load capacitance in pF CS= max. switch capacitance in pF VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PZH
/ t
PZL
turn “ON” time E or Sn to V
OS
CL= 15 pF ; RL=1 kΩ; VCC=5 V
28 18 ns
t
PHZ
/ t
PLZ
turn “OFF” time E or Sn to V
OS
21 13 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per switch notes 1 and 2 57 57 pF
C
S
max. switch capacitance
independent (Y) 5 5 pF common (Z) 12 12 pF
December 1990 3
Philips Semiconductors Product specification
Dual 4-channel analog multiplexer/demultiplexer
74HC/HCT4052
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 5, 2, 4 2Y
0
to 2Y
3
independent inputs/outputs
6
E enable input (active LOW)
7V
EE
negative supply voltage 8 GND ground (0 V) 10, 9 S
0
, S
1
select inputs 12, 14, 15, 11 1Y
0
to 1Y
3
independent inputs/outputs 13, 3 1Z, 2Z common inputs/outputs 16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
Dual 4-channel analog multiplexer/demultiplexer
74HC/HCT4052
Fig.4 Functional diagram.
APPLICATIONS
Analog multiplexing and demultiplexing
Digital multiplexing and
demultiplexing
Signal gating
FUNCTION TABLE
Notes
1. H = HIGH voltage level L = LOW voltage level X = don’t care
INPUTS
CHANNEL
ON
ES
1
S
0
L L L L
L
L H H
L
H
L
H
nY0− nZ nY1− nZ nY2− nZ nY3− nZ
H X X none
Fig.5 Schematic diagram (one switch).
December 1990 5
Philips Semiconductors Product specification
Dual 4-channel analog multiplexer/demultiplexer
74HC/HCT4052
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to VEE= GND (ground = 0 V)
Note to ratings
1. To avoid drawing V
CC
current out of terminals nZ, when switch current flows in terminals nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals nZ, no VCC current will flow out of terminals nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
V
CC
DC supply voltage 0.5 +11.0 V
±I
IK
DC digital input diode current 20 mA for VI<−0.5 V or VI> VCC +0.5 V
±I
SK
DC switch diode current 20 mA for VS<−0.5 V or VS> VCC +0.5 V
±I
S
DC switch current 25 mA for 0.5 V < VS< VCC +0.5 V
±I
EE
DC VEE current 20 mA
±I
CC
; ±I
GND
DC VCC or GND current 50 mA
T
stg
storage temperature range 65 +150 °C
P
tot
power dissipation per package for temperature range: 40 to +125 °C
74HC/HCT plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K
P
S
power dissipation per switch 100 mW
SYMBOL PARAMETER
74HC 74HCT
UNIT CONDITIONS
min. typ. max. min. typ. max.
V
CC
DC supply voltage VCC−GND 2.0 5.0 10.0 4.5 5.0 5.5 V see Fig.6 and Fig.7
V
CC
DC supply voltage VCC−V
EE
2.0 5.0 10.0 2.0 5.0 10.0 V see Fig.6 and Fig.7
V
I
DC input voltage range GND V
CC
GND V
CC
V
V
S
DC switch voltage range V
EE
V
CCVEE
V
CC
V
T
amb
operating ambient temperature range 40 +85 40 +85 °C see DC and AC
CHARACTERISTICS
T
amb
operating ambient temperature range 40 +125 40 +125 °C
t
r
, t
f
input rise and fall times
6.0
1000 500 400 250
6.0 500 ns
VCC= 2.0 V VCC= 4.5 V VCC= 6.0 V VCC= 10.0 V
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