Philips 74HCT4046AU, 74HCT4046ADB, 74HCT4046AD, 74HC4046AU, 74HC4046APW Datasheet

DATA SH EET

Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06

1997 Nov 25

INTEGRATED CIRCUITS

74HC/HCT4046A

Phase-locked-loop with VCO

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

1997 Nov 25 2

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

FEATURES

• Low power consumption

• Centre frequency of up to 17 MHz (typ.) at VCC= 4.5 V

• Choice of three phase comparators: EXCLUSIVE-OR;

edge-triggered JK flip-flop;
edge-triggered RS flip-flop

• Excellent VCO frequency linearity

• VCO-inhibit control for ON/OFF keying and for low

standby power consumption

• Minimal frequency drift

• Operating power supply voltage range:

VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V

• Zero voltage offset due to op-amp buffering

• Output capability: standard

• I

CC

category: MSI.

GENERAL DESCRIPTION

The 74HC/HCT4046A are high-speed Si-gate CMOS
devices and are pin compatible with the “4046” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

The 74HC/HCT4046A are phase-locked-loop circuits that
comprise a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2 and PC3)
with a common signal input amplifier and a common
comparator input.

The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the “4046A”
forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear op-amp
techniques.

The VCO requires one external capacitor C1 (between
C1

A

and C1B) and one external resistor R1 (between
R1and GND) or two external resistors R1 and R2
(between R1and GND, and R2and GND). Resistor R1
and capacitor C1 determine the frequency range of the
VCO. Resistor R2 enables the VCO to have a frequency
offset if required.

The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is

provided at pin 10 (DEM

OUT

). In contrast to conventional

techniques where the DEM

OUT

voltage is one threshold
voltage lower than the VCO input voltage, here the
DEM

OUT

voltage equals that of the VCO input. If

DEM

OUT

is used, a load resistor (RS) should be connected

from DEM

OUT

to GND; if unused, DEM

OUT

should be left

open. The VCO output (VCO

OUT

) can be connected
directly to the comparator input (COMPIN), or connected
via a frequency-divider. The VCO output signal has a duty
factor of 50% (maximum expected deviation 1%), if the
VCO input is held at a constant DC level. A LOW level at
the inhibit input (INH) enables the VCO and demodulator,
while a HIGH level turns both off to minimize standby
power consumption.

The only difference between the HC and HCT versions is
the input level specification of the INH input. This input
disables the VCO section. The sections of the comparator
are identical, so that there is no difference in the
SIGIN(pin 14) or COMPIN(pin 3) inputs between the HC
and HCT versions.

Phase comparators

The signal input (SIG

IN

) can be directly coupled to the
self-biasing amplifier at pin 14, provided that the signal
swing is between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.

Phase comparator 1 (PC1)

This is an EXCLUSIVE-OR network. The signal and
comparator input frequencies (fi) must have a 50% duty
factor to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (f

r

=2fi) is

suppressed, is:

where V

DEMOUT

is the demodulator output at pin 10;

V

DEMOUT=VPC1OUT

(via low-pass filter).

The phase comparator gain is:
The average output voltage from PC1, fed to the VCO

input via the low-pass filter and seen at the demodulator
output at pin 10 (V

DEMOUT

), is the resultant of the phase

differences of signals (SIG

IN

) and the comparator input

(COMP

IN

) as shown in Fig.6. The average of V

DEMOUT

is

equal to

1

⁄2VCCwhen there is no signal or noise at

SIG

IN

and with this input the VCO oscillates at the centre

frequency (f

o

). Typical waveforms for the PC1 loop locked

at f

o

are shown in Fig.7.

V

DEMOUT

V

CC

π

---------- -

φ

SIGINφCOMPIN

–()=

K

p

V

CC

π

---------- -

Vr⁄()

˙

.=

1997 Nov 25 3

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

The frequency capture range (2fc) is defined as the
frequency range of input signals on which the PLL will lock
if it was initially out-of-lock. The frequency lock range
(2fL) is defined as the frequency range of input signals on
which the loop will stay locked if it was initially in lock. The
capture range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass
filter characteristics and can be made as large as the lock
range.
This configuration retains lock even with very noisy input
signals. Typical behaviour of this type of phase
comparator is that it can lock to input frequencies close to
the harmonics of the VCO centre frequency.

Phase comparator 2 (PC2)

This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIGINand COMPINare not important. PC2
comprises two D-type flip-flops, control-gating and a
3-state output stage. The circuit functions as an up-down
counter (Fig.5) where SIG

IN

causes an up-count and

COMP

IN

a down-count. The transfer function of PC2,

assuming ripple (f

r=fi

) is suppressed,

is:

where V

DEMOUT

is the demodulator output at pin 10;

V

DEMOUT=VPC2OUT

(via low-pass filter).

The phase comparator gain is:

V

DEMOUT

is the resultant of the initial phase differences of
SIGINand COMPINas shown in Fig.8. Typical waveforms
for the PC2 loop locked at foare shown in Fig.9.

When the frequencies of SIGINand COMPINare equal but
the phase of SIGINleads that of COMPIN, the p-type
output driver at PC2

OUT

is held “ON” for a time

corresponding to the phase difference (φ

DEMOUT

). When
the phase of SIGINlags that of COMPIN, the n-type driver
is held “ON”.

When the frequency of SIGINis higher than that of
COMPIN, the p-type output driver is held “ON” for most of
the input signal cycle time, and for the remainder of the
cycle both n and p- type drivers are ”OFF” (3-state). If the
SIGINfrequency is lower than the COMPINfrequency, then
it is the n-type driver that is held “ON” for most of the cycle.
Subsequently, the voltage at the capacitor (C2) of the
low-pass filter connected to PC2

OUT

varies until the signal

V

DEMOUT

V

CC

4π

---------- -

φ

SIGINφCOMPIN

–()=

K

p

V

CC

4π

---------- -

Vr⁄().=

and comparator inputs are equal in both phase and
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in 3-state and the VCO input
at pin 9 is a high impedance. Also in this condition, the
signal at the phase comparator pulse output (PCP

OUT

) is a
HIGH level and so can be used for indicating a locked
condition.

Thus, for PC2, no phase difference exists between
SIGINand COMPINover the full frequency range of the
VCO. Moreover, the power dissipation due to the low-pass
filter is reduced because both p and n-type drivers are
“OFF” for most of the signal input cycle. It should be noted
that the PLL lock range for this type of phase comparator
is equal to the capture range and is independent of the
low-pass filter. With no signal present at SIGINthe
VCO adjusts, via PC2, to its lowest frequency.

Phase comparator 3 (PC3)

This is a positive edge-triggered sequential phase detector
using an RS-type flip-flop. When the PLL is using this
comparator, the loop is controlled by positive signal
transitions and the duty factors of SIGINand COMPINare
not important. The transfer characteristic of PC3,
assuming ripple (f

r=fi

) is suppressed,

is:

where V

DEMOUT

is the demodulator output at pin 10;

V

DEMOUT=VPC3OUT

(via low-pass filter).

The phase comparator gain is:

The average output from PC3, fed to the VCO via the
low-pass filter and seen at the demodulator output at
pin 10 (V

DEMOUT

), is the resultant of the phase differences
of SIGINand COMPINas shown in Fig.10. Typical
waveforms for the PC3 loop locked at foare shown in
Fig.11.

The phase-to-output response characteristic of PC3
(Fig.10) differs from that of PC2 in that the phase angle
between SIGINand COMPINvaries between 0° and
360° and is 180° at the centre frequency. Also PC3 gives
a greater voltage swing than PC2 for input phase
differences but as a consequence the ripple content of the
VCO input signal is higher. The PLL lock range for this type
of phase comparator and the capture range are dependent
on the low-pass filter. With no signal present at SIGINthe
VCO adjusts, via PC3, to its lowest frequency.

V

DEMOUT

V

CC

2π

---------- -

φ

SIGINφCOMPIN

–()=

K

p

V

CC

2π

---------- -

Vr⁄().=

1997 Nov 25 4

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C

Notes

1. C

PD

is used to determine the dynamic power dissipation (PDin µW):

PD=CPD× V

CC

2

× fi+ ∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz.
fo= output frequency in MHz.
CL= output load capacitance in pF.
VCC= supply voltage in V.
∑ (CL× V

CC

2

× fo) = sum of outputs.

2. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections see Figs 22, 23 and 24.

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

APPLICATIONS

• FM modulation and demodulation

• Frequency synthesis and multiplication

• Frequency discrimination

• Tone decoding

• Data synchronization and conditioning

• Voltage-to-frequency conversion

• Motor-speed control.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

f

o

VCO centre frequency C1 = 40 pF; R1 = 3 kΩ;VCC= 5 V 19 19 MHz

C

I

input capacitance (pin 5) 3.5 3.5 pF

C

PD

power dissipation capacitance per
package

notes 1 and 2 24 24 pF

1997 Nov 25 5

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 PCP

OUT

phase comparator pulse output

2 PC1

OUT

phase comparator 1 output

3 COMP

IN

comparator input

4 VCO

OUT

VCO output
5 INH inhibit input
6C1

A

capacitor C1 connection A
7C1

B

capacitor C1 connection B
8 GND ground (0 V)
9 VCO

IN

VCO input
10 DEM

OUT

demodulator output
11 R

1

resistor R1 connection
12 R

2

resistor R2 connection
13 PC2

OUT

phase comparator 2 output
14 SIG

IN

signal input
15 PC3

OUT

phase comparator 3 output
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

1997 Nov 25 6

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

MGA847

PHASE

COMPARATOR

2

LOCK

DETECTOR

PC2

OUTLD13

1

identical to 4046A

C

LD

C

CLD

15

7046A

PHASE

COMPARATOR

2

PC2

OUT 13

PHASE

COMPARATOR

3

PC3

OUT 15

PHASE

COMPARATOR

1

PC1

OUT

2

PCP

OUT

1

SIG

IN

COMP

IN

V

CO OUT

C1AC1

B

DEM

OUTINH

VCO

IN

R

2

R

1

R2

12

11

314476

5109

(a)

(b)

C1

4046A

VCO

R

S

R1

R4

R3

C2

Fig.4 Functional diagram.

(a) (b)

Fig.5 Logic diagram.

1997 Nov 25 7

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

Fig.6 Phase comparator 1: average output voltage versus input phase difference.

V

DEMOUT=VPC2OUT

=

φ

DEMOUT

=(φ

SIGIN−φCOMPIN

).

V

CC

π

---------- -

φ

SIGINφCOMPIN

–()

Fig.7 Typical waveforms for PLL using phase comparator 1, loop locked at fo.

Fig.8 Phase comparator 2: average output voltage versus input phase difference.

V

DEMOUT=VPC2OUT

=

φ

DEMOUT

=(φ

SIGIN

−φC

OMPIN

).

V

CC

4π

---------- -

φ

SIGINφCOMPIN

–()

1997 Nov 25 8

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

Fig.9 Typical waveforms for PLL using phase comparator 2, loop locked at fo.

Fig.10 Phase comparator 3: average output voltage versus input phase difference:

V

DEMOUT=VPC3OUT

=

φ

DEMOUT

=(φ

SIGIN−φCOMPIN

).

V

CC

2π

---------- -

φ

SIGINφCOMPIN

–()

Fig.11 Typical waveforms for PLL using phase comparator 3, loop locked at fo.

1997 Nov 25 9

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

74HC 74HCT

UNIT CONDITIONS

min. typ. max. min. typ. max.

V

CC

DC supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 V

V

CC

DC supply voltage if VCO
section is not used

2.0 5.0 6.0 4.5 5.0 5.5 V

V

I

DC input voltage range 0 V

CC

0V

CC

V

V

O

DC output voltage range 0 V

CC

0V

CC

V

T

amb

operating ambient
temperature range

−40 +85 −40 +85 °C see DC and AC
CHARACTERISTICS

T

amb

operating ambient
temperature range

−40 +125 −40 +125 °C

t

r,tf

input rise and fall times (pin 5) 6.0 1000 6.0 500 ns VCC= 2.0 V

6.0 500 6.0 500 ns V

CC

= 4.5 V

6.0 400 6.0 500 ns V

CC

= 6.0 V

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

V

CC

DC supply voltage −0.5 +7 V

±I

IK

DC input diode current 20 mA for VI<−0.5 V or VI> VCC+ 0.5 V

±I

OK

DC output diode current 20 mA for VO<−0.5 V or VO> VCC+ 0.5 V

±I

O

DC output source or sink
current

25 mA for −0.5 V < VO< VCC+ 0.5 V

±I

CC

; ±I

GND

DC VCCor GND current 50 mA

T

stg

storage temperature range −65 +150 °C

P

tot

power dissipation per package

plastic DIL 750 mW

for temperature range: − 40 to +125 °C
74HC/HCT
above + 70 °C: derate linearly with 12 mW/K

plastic mini-pack (SO) 500 mW above + 70 °C: derate linearly with 8 mW/K

1997 Nov 25 10

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

DC CHARACTERISTICS FOR 74HC
Quiescent supply current

Voltages are referenced to GND (ground = 0 V)

Phase comparator section

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC V

CC

(V)

OTHER

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

I

CC

quiescent supply
current (VCO
disabled)

8.0 80.0 160.0 µA 6.0

pins 3, 5, and 14 at VCC;
pin 9 at GND; I

I

at pins

3 and 14 to be excluded

SYM­BOL

PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC V

CC

(V)

V

I

OTHER

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

V

IH

DC coupled

HIGH level input voltage
SIGIN, COMP

IN

1.5 1.2 1.5 1.5 V 2.0

3.15 2.4 3.15 3.15 4.5

4.2 3.2 4.2 4.2 6.0

V

IL

DC coupled

LOW level input voltage
SIGIN, COMP

IN

0.8 0.5 0.5 0.5 V 2.0

2.1 1.35 1.35 1.35 4.5

2.8 1.8 1.8 1.8 6.0

V

OH

HIGH level output voltage

PCP

OUT

,PC

nOUT

1.9 2.0 1.9 1.9 V 2.0 V

IH

or
V

IL

−IO=20µA

4.4 4.5 4.4 4.4 4.5 −I

O

=20µA

5.9 6.0 5.9 5.9 6.0 −I

O

=20µA

V

OH

HIGH level output voltage

PCP

OUT

,PC

nOUT

3.98 4.32 3.84 3.7 V 4.5 V

IH

or
V

IL

−IO= 4.0 mA

5.48 5.81 5.34 5.2 6.0 −I

O

= 5.2 mA

V

OL

LOW level output voltage

PCP

OUT

,PC

nOUT

0 0.1 0.1 0.1 V 2.0 V

IH

or
V

IL

IO=20µA

0 0.1 0.1 0.1 4.5 I

O

=20µA

0 0.1 0.1 0.1 6.0 I

O

=20µA

V

OL

LOW level output voltage

PCP

OUT

,PC

nOUT

0.15 0.26 0.33 0.4 V 4.5 V

IH

or
V

IL

IO= 4.0 mA

0.16 0.26 0.33 0.4 6.0 I

O

= 5.2 mA

±I

I

input leakage current

SIGIN, COMP

IN

3.0 4.0 5.0 µA 2.0 V

CC

or

GND

7.0 9.0 11.0 3.0

18.0 23.0 27.0 4.5

30.0 38.0 45.0 6.0

±I

OZ

3-state

OFF-state current
PC2

OUT

0.5 5.0 10.0 µA 6.0 V

IH

or
V

IL

VO=VCCor
GND

1997 Nov 25 11

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

VCO section

Voltages are referenced to GND (ground = 0 V)

R

I

input resistance

SIGIN, COMP

IN

800 kΩ 3.0 V

I

at self-bias
operating point;
∆ V

I

= 0.5 V;
see Figs 12, 13
and 14

250 kΩ 4.5
150 kΩ 6.0

SYM­BOL

PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC V

CC

(V)

V

I

OTHER

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

V

IH

HIGH level

input voltage
INH

2.1 1.7 2.1 2.1 V 3.0

3.15 2.4 3.15 3.15 4.5

4.2 3.2 4.2 4.2 6.0

V

IL

LOW level

input voltage
INH

1.3 0.9 0.9 0.9 V 3.0

2.1 1.35 1.35 1.35 4.5

2.8 1.8 1.8 1.8 6.0

V

OH

HIGH level

output voltage
VCO

OUT

2.9 3.0 2.9 2.9 V 3.0 V

IH

or
V

IL

−IO=20µA

4.4 4.5 4.4 4.4 4.5 −I

O

=20µA

5.9 6.0 5.9 5.9 6.0 −I

O

=20µA

V

OH

HIGH level

output voltage
VCO

OUT

3.98 4.32 3.84 3.7 V 4.5 V

IH

or
V

IL

−IO= 4.0 mA

5.48 5.81 5.34 5.2 6.0 −I

O

= 5.2 mA

V

OL

LOW level

output voltage
VCO

OUT

0 0.1 0.1 0.1 V 3.0 V

IH

or
V

IL

IO=20µA

0 0.1 0.1 0.1 4.5 I

O

=20µA

0 0.1 0.1 0.1 6.0 I

O

=20µA

V

OL

LOW level

output voltage
VCO

OUT

0.15 0.26 0.33 0.4 V 4.5 V

IH

or
V

IL

IO= 4.0 mA

0.16 0.26 0.33 0.4 6.0 I

O

= 5.2 mA

V

OL

LOW level output

voltage C1A,C1

B

0.40 0.47 0.54 V 4.5 V

IH

or
V

IL

IO= 4.0 mA

0.40 0.47 0.54 6.0 I

O

= 5.2 mA

±I

I

input leakage
current

INH, VCO

IN

0.1 1.0 1.0 µA 6.0 V

CC

or
GND

R1 resistor range 3.0 300 kΩ 3.0 note 1

3.0 300 4.5

3.0 300 6.0

SYM­BOL

PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC V

CC

(V)

V

I

OTHER

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.