Philips 74HCT4024U, 74HCT4024PW, 74HCT4024N, 74HCT4024D, 74HC4024N Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4024

7-stage binary ripple counter

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
7-stage binary ripple counter	74HC/HCT4024

FEATURES

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4024 are high-speed Si-gate CMOS devices and are pin compatible with the “4024” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT4024 are 7-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The counter advances on the HIGH-to-LOW transition of CP.

A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP.

Each counter stage is a static toggle flip-flop.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

APPLICATIONS

·Frequency dividing circuits

·Time delay circuits

SYMBOL		PARAMETER			CONDITIONS	TYPICAL		UNIT
						HC	HCT
tPHL/ tPLH		propagation delay		to Q0	CL = 15 pF; VCC = 5 V	14	14	ns
			CP
fmax		maximum clock frequency				90	70	MHz
CI		input capacitance				3.5	3.5	pF
CPD		power dissipation capacitance per package			notes 1 and 2	25	27	pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC	the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors					Product specification
7-stage binary ripple counter					74HC/HCT4024
PIN DESCRIPTION
PIN NO.		SYMBOL		NAME AND FUNCTION
1				clock input (HIGH-to-LOW, edge-triggered)
		CP
2		MR		master reset input (active HIGH)
12, 11, 9, 6, 5, 4, 3	Q0 to Q6			parallel outputs
7		GND		ground (0 V)
8, 10, 13		n.c.		not connected
14		VCC		positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

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