Philips 74HCT4024U, 74HCT4024PW, 74HCT4024N, 74HCT4024D, 74HC4024N Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT4024

7-stage binary ripple counter

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

7-stage binary ripple counter 74HC/HCT4024

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4024 are high-speed Si-gate CMOS
devices and are pin compatible with the “4024” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

The 74HC/HCT4024 are 7-stage binary ripple counters
with a clock input (

CP), an overriding asynchronous
master reset input (MR) and seven fully buffered parallel
outputs (Q0to Q6).

The counter advances on the HIGH-to-LOW transition of
CP.

A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.

Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

APPLICATIONS

• Frequency dividing circuits

• Time delay circuits

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay CP to Q

0

CL= 15 pF; VCC= 5 V 14 14 ns

f

max

maximum clock frequency 90 70 MHz

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per package notes 1 and 2 25 27 pF

December 1990 3

Philips Semiconductors Product specification

7-stage binary ripple counter 74HC/HCT4024

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1

CP clock input (HIGH-to-LOW, edge-triggered)
2 MR master reset input (active HIGH)
12, 1 1, 9, 6, 5, 4, 3 Q

0

to Q

6

parallel outputs
7 GND ground (0 V)
8, 10, 13 n.c. not connected
14 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.