Philips 74HCT85U, 74HCT85NB, 74HCT85N, 74HCT85DB, 74HCT85D Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT85

4-bit magnitude comparator

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

4-bit magnitude comparator 74HC/HCT85

FEATURES

• Serial or parallel expansion without extra gating

• Magnitude comparison of any binary words

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT85 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT85 are 4-bit magnitude comparators that
can be expanded to almost any length. They perform
comparison of two 4-bit binary, BCD or other monotonic
codes and present the three possible magnitude results at
the outputs (Q

A>B

, Q

A=B

and Q

A<B

). The 4-bit inputs are

weighted (A0 to A3 and B0 to B3), where A3 and B3 are the
most significant bits.

The operation of the “85” is described in the function table,
showing all possible logic conditions. The upper part of the
table describes the normal operation under all conditions
that will occur in a single device or in a series expansion
scheme. In the upper part of the table the three outputs are
mutually exclusive. In the lower part of the table, the
outputs reflect the feed forward conditions that exist in the
parallel expansion scheme.

For proper compare operation the expander inputs (I

A>B

,

I

A=B

and I

A<B

) to the least significant position must be

connected as follows: I

A<B=IA>B

= = LOW and

I

A=B

= HIGH.
For words greater than 4-bits, units can be cascaded by
connecting outputs Q

A<B

, Q

A>Β

and Q

A=B

to the

corresponding inputs of the significant comparator.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+ ∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL/ tPLH

propagation delay CL= 15 pF; VCC=5 V
A

n

, Bn to Q

A>B

, Q

A<B

20 22 ns

A

n

, Bn to Q

A=B

18 20 ns

I

A<B,

, I

A=B

, I

A>B

to Q

A<B

, Q

A>B

15 15 ns

I

A=B

to Q

A=B

11 15 ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per package notes 1 and 2 18 20 pF

December 1990 3

Philips Semiconductors Product specification

4-bit magnitude comparator 74HC/HCT85

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

2I

A<B

A< B expansion input

3I

A=B

A = B expansion input

4I

A>B

A>B expansion input

5Q

A>B

A> B output

6Q

A=B

A = B output

7Q

A<B

A<B output
8 GND ground (0 V)
9, 11, 14, 1, B

0

to B

3

word B inputs
10, 12, 13, 15 A

0

to A

3

word A inputs
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.