Philips 74HCT7731N, 74HCT7731D, 74HC7731N, 74HC7731D Datasheet

INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7731
Quad 64-bit static shift register
Product specification File under Integrated Circuits, IC06
September 1993
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
FEATURES
Frequency range DC to 100 MHz.
Separate serial data inputs
Cascadable
Functionally compatible with
HEF 4731
Includes recycling mode
Direct shift out
Output capability: Standard
ICC category: LSI.
APPLICATIONS
Data storage
Delay line.
GENERAL DESCRIPTION
The HC/HCT7731 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A.
The HC/HCT7731 are quad 64-bit static shift registers with a recycling mode. Each register has separate data inputs D
to Dd, clock inputs CP
a
to CPd and data outputs Qa to Qd. Data shifts one place towards the output, each LOW to HIGH transition of the clock pulse. Each recycling mode input controls two registers RECab for registers A and B and RECcd for registers C and D. When the REC input is HIGH, the device is in the recycling mode and data at the output is shifted back into the input of the register, so after 64 clock pulses the contents of a register is again in its original position. This enables the user to tap off data from any position. When the REC input is LOW external data can be shifted in.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr = tf = 6 ns.
amb
TYP.
SYMBOL PARAMETER CONDITIONS
HC HCT
t
PHL/tPLH
f
max
propagation delay
CP
to Q
a-d
a-d
maximum clock
CL = 15 pF; VCC = 5 V
15 20 ns
100 100 MHz
frequency
C
I
C
PD
input capacitance 3.5 3.5 pF power dissipation
capacitance per register
notes 1, 2 and 3
58 61 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD = (CPD x V
2
x fi) + (CL + V
CC
CC
2
x fo) + (I
pull-up
x VCC) where: fi = input frequency in MHz. fo = output frequency in MHz. VCC = supply voltage in V. CL = output load capacitance in pF. I
= pull-up currents in µA.
pull-up
2. For HC the condition is VI = GND to V
CC
For HCT the condition is VI = GND to VCC− 1.5 V.
3. See also power dissipation information.
a
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
PINS PIN POSITION MATERIAL CODE
PACKAGE
74HC/HCT7731N 16 DIL plastic SOT38Z 74HC/HCT7731D 16 SO16 plastic SOT109A
UNIT
September 1993 2
Philips Semiconductors Product specification
Quad 64-bit static shift register 74HC/HCT7731
PINNING
SYMBOL PIN DESCRIPTION
Q
to Q
a
d
CP
to CP
D
to D
a
REC
a
, REC
ab
d
d
cd
GND 8 ground (0 V) V
CC
1, 7, 9, 15 data outputs 2, 6, 10, 14 clock inputs 3, 5, 11, 13 data inputs
4, 12 recycled enable input
16 positive supply
handbook, halfpage
REC
Q
CP
D
D
CP
Q
GND
1
a
2
a
3
a
4
ab
b b b
7731
5 6 7 8
MBA341
V
16
CC
Q
15
d
CP
14
d
D
13
d
12
REC
cd
D
11
c
CP
10
c
Q
9
c
handbook, full pagewidth
Fig.1 Pin configuration.
D
a
3
CP
a
2
REC
ab
4
D
5
b
CP
b
6
D
c
11
CP
c
10
REC
cd
12
D
13
d
CP
d
14
MUX
MUX
MUX
MUX
64 - BIT
STATIC SHIFT
REGISTER
64 - BIT
STATIC SHIFT
REGISTER
64 - BIT
STATIC SHIFT
REGISTER
64 - BIT
STATIC SHIFT
REGISTER
Q
a
1
Q
7
b
Q
9
c
Q
15
d
Fig.2 Functional diagram.
September 1993 3
MBA342
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