Philips Semiconductors Advanced BiCMOS Products |
Product specification |
|
|
|
|
Synchronizing dual D-type flip-flop
74ABT5074
with metastable immune characteristics
FEATURES
•Metastable immune characteristics
•Pin compatible with 74F74 and 74F5074
•Typical fMAX = 200MHz
•Output skew guaranteed less than 2.0ns
•High source current (IOH = 15mA) ideal for clock driver applications
•Output capability: +20mA/±15mA
•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set and reset inputs; also true and complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and operate independently of the clock (CPn) input. Data must be stable just one setup time prior to the low-to-high transition of the clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output.
The 74ABT5074 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74ABT5074 are:
t @ 94ps and To @ 1.3 × 107 sec
PIN CONFIGURATION
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RD0 |
1 |
|
|
|
14 |
VCC |
|||||||||
|
|
|
|
|
D0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
|
|
|
13 |
|
RD1 |
||||
|
CP0 |
|
|
|
|
|
D1 |
||||||||
|
3 |
|
|
|
12 |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
CP1 |
|||
|
|
SD0 |
4 |
|
|
|
11 |
||||||||
|
|
Q0 |
|
|
|
|
|
|
|
|
|
||||
|
|
5 |
|
|
|
10 |
|
SD1 |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
Q1 |
|||
|
|
|
Q0 |
6 |
|
|
|
9 |
|||||||
GND |
|
|
|
|
|
|
|
|
|
||||||
7 |
|
|
|
8 |
|
Q1 |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SA00001 |
PIN DESCRIPTION |
|
|||||||
|
|
|
|
|
|
|
|
|
PIN NUMBER |
|
SYMBOL |
NAME AND FUNCTION |
|||||
|
|
|
|
|
|
|
|
|
2, 12 |
|
|
D0, D1 |
Data inputs |
||||
|
|
|
|
|
|
|
|
|
3, 11 |
|
CP0, CP1 |
Clock inputs (active rising edge) |
|||||
|
|
|
|
|
|
|
|
|
4, 10 |
|
|
|
|
|
|
|
Set inputs (active-Low) |
|
SD0, SD1 |
|||||||
|
|
|
|
|
|
|
||
1, 13 |
|
|
|
|
|
|
|
Reset inputs (active-Low) |
|
RD0, RD1 |
|||||||
|
|
|
|
|
|
|
|
|
5, 9 |
|
Q0, Q1 |
Data outputs (active-Low), |
|||||
|
non-inverting |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Data outputs (active-Low), |
6, 8 |
|
Q0, Q1 |
||||||
|
inverting |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
7 |
|
|
|
GND |
Ground (0V) |
|||
|
|
|
|
|
|
|||
14 |
|
|
|
VCC |
Positive supply voltage |
|||
where t represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
|||
Tamb = 25°C; GND = 0V |
|||||||
|
|
|
|
|
|
||
tPLH |
Propagation delay |
CL = 50pF; VCC = 5V |
2.8 |
ns |
|||
|
|
|
|
|
|||
tPHL |
CPn to Qn or Qn |
2.4 |
|||||
|
|
||||||
CIN |
Input capacitance |
VI = 0V or VCC |
3 |
pF |
|||
ICC |
Total supply current |
Outputs disabled; VCC =5.5V |
2 |
mA |
|||
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
ORDER CODE |
DRAWING NUMBER |
|
|
|
|
14-pin plastic DIP |
±40°C to +85°C |
74ABT5074N |
SOT27-1 |
|
|
|
|
14-pin plastic SOL |
±40°C to +85°C |
74ABT5074D |
SOT108-1 |
|
|
|
|
14-pin plastic shrink small outline SSOP Type II |
±40°C to +85°C |
74ABT5074DB |
SOT337-1 |
|
|
|
|
14-pin plastic thin shrink small outline (TSSOP) Type I |
±40°C to +85°C |
74ABT5074PW |
SOT402-1 |
|
|
|
|
December 15, 1994 |
1 |
853-1775 14470 |
Philips Semiconductors Advanced BiCMOS Products |
Product specification |
|
|
|
|
Synchronizing dual D-type flip-flop
74ABT5074
with metastable immune characteristics
LOGIC SYMBOL |
|
|
|
|
|
|
|
|
|
|
IEC/IEEE SYMBOL |
|
|
|||||||
|
|
|
|
2 |
12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
4 |
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S |
5 |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
3 |
|
CP0 |
D0 |
D1 |
|
|
|
|
3 |
|
|
C1 |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
2 |
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
4 |
|
SD0 |
|
|
|
|
|
|
|
|
|
|
1D |
6 |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
1 |
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
1 |
|
RD0 |
|
|
|
|
|
|
|
|
|
|
R |
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
11 |
|
CP1 |
|
|
|
|
|
|
|
|
10 |
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
10 |
|
SD1 |
|
|
|
|
|
|
|
|
|
|
S |
9 |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
11 |
|
|
|||||||||
13 |
|
RD1 |
|
|
|
|
|
|
|
|
|
|
C2 |
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
12 |
|
|
|
|
|||||||
|
|
Q0 |
Q0 |
Q1 Q1 |
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
2D |
8 |
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
13 |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
R |
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC = Pin 14 |
5 |
6 |
9 |
8 |
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
GND = Pin 7 |
|
|
|
|
|
|
|
|
SA00002 |
|
|
|
|
|
|
|
|
|
SA00003 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
LOGIC DIAGRAM
SD |
4, 10 |
|
|
|
|
RD |
1, 13 |
5, 9 |
|
Q |
|
|
3, 11 |
6, 8 |
CP |
Q |
|
|
|
|
D |
2, 12 |
|
|
|
|
VCC = Pin 14 |
|
|
GND = Pin 7 |
|
|
|
|
SF00048 |
FUNCTION TABLE
|
|
|
|
INPUTS |
|
OUTPUTS |
OPERATING |
|||||
|
|
|
|
|
|
|
|
|
|
MODE |
||
|
|
|
|
|
|
CP |
D |
Q |
|
|
|
|
|
SD |
RD |
Q |
|||||||||
|
|
|
|
|
|
|
|
|
|
|||
|
L |
|
H |
X |
X |
H |
|
L |
Asynchronous set |
|||
|
|
|
|
|
|
|
|
|
|
|||
|
H |
|
L |
X |
X |
L |
|
H |
Asynchronous reset |
|||
|
|
|
|
|
|
|
|
|
|
|||
|
L |
|
L |
X |
X |
L |
|
H |
Undetermined* |
|||
|
|
|
|
|
|
|
|
|
|
|||
|
H |
|
H |
↑ |
h |
H |
|
L |
Load º1º |
|||
|
|
|
|
|
|
|
|
|
|
|||
|
H |
|
H |
↑ |
l |
L |
|
H |
Load º0º |
|||
|
|
|
|
|
|
|
|
|
||||
|
H |
|
H |
↑ |
X |
NC |
NC |
Hold |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
NOTES:
H = High voltage level
h= High voltage level one setup time prior to low-to-high clock transition
L = Low voltage level
l= Low voltage level one setup time prior to low-to-high clock transition
NC= |
No change from the previous setup |
X = |
Don't care |
↑= Low-to-high clock transition
↑= Not low-to-high clock transition
*= This setup is unstable and will change when either set or reset return to the high level
December 15, 1994 |
2 |
Philips Semiconductors Advanced BiCMOS Products |
Product specification |
|
|
|
|
Synchronizing dual D-type flip-flop
74ABT5074
with metastable immune characteristics
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term `metastable immune' to describe characteristics of some of the products in its family. By running two independent signal generators (see Figure 1) at nearly the same frequency (in this case 10MHz clock and 10.02MHz data) the device-under-test can often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform. An experiment was run by continuously operating the devices in the region where metastability will occur.
SIGNAL |
D |
|
Q |
TRIGGER |
GENERATOR |
|
|||
|
|
|
|
|
|
|
|
|
DIGITAL |
|
|
|
|
SCOPE |
SIGNAL |
|
CP |
Q |
INPUT |
GENERATOR |
|
|||
|
|
|||
|
|
|
|
SA00004 |
After determining the T0 and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74ABT5074 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74ABT5074 7 nanoseconds after the clock edge. He simply plugs his number into the following equation:
MTBF = e(t'/τ)/ TO*fC*fI
In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' > h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Figure 2 it is clear that the MTBF is greater than 1010 seconds. Using the above formula the actual MTBF is 1.69 × 1010 seconds or about 535 years.
Figure 1. Test Setup
|
10,000 YEARS |
|
MTBF |
100 YEARS |
|
(SECONDS) |
||
|
||
|
ONE YEAR |
|
|
ONE WEEK |
E13 |
E6 |
E8 |
E10 |
E12 |
E14 |
E15 |
= fc*fi |
E12 |
|
|
|
|
|
|
|
E11 |
|
|
|
|
|
|
|
E10 |
|
|
|
|
|
|
|
E9 |
|
|
|
|
|
|
|
E8 |
|
|
|
|
|
|
|
E7 |
|
|
|
|
|
|
|
E6 |
|
|
|
|
|
|
|
E5 |
|
|
|
|
|
|
|
4 |
5 |
6 |
|
7 |
|
|
8 |
|
t' (NANOSECONDS) |
|
VCC = 5V, Tamb = 25°C, t =94ps, To = 1.3x107 sec |
MTBF = e(t'/τ)/TO*fC*fI |
SA00005 |
Figure 2. |
Mean Time Between Failures (MTBF) versus t' |
|
December 15, 1994 |
3 |
Loading...