Philips 74f711a, 74f 711, 74f, 712a, 712 Service manual
INTEGRATED CIRCUITS
74F711A, 74F711-1, 74F712A, 74F712-1
Multiplexers
Product specification
IC15 Data Handbook
1990 Dec 13
Philips Semiconductors Product specification
74F71 1A/74F711–1/
Multiplexers
74F711A Quint 2-to-1 Data Selector Multiplexer (3-State)
74F711-1 Quint 2-to-1 Data Selector Multiplexer with 30 Equivalent Output Termination Impedance (3-State)
74F712A Quint 3-to-1 Data Selector Multiplexer
74F712-1 Quint 3-to-1 Data Selector Multiplexer with 30
Equivalent Output Termination Impedance
74F712A/74F712–1
FEATURES for 74F711A/74F711-1
•Consists of five 2-to-1 Multiplexers
•High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
•Designed for address multiplexing of dynamic RAM and other
applications
•Output inverting/non-inverting option
•30 termination impedance on each output – 74F711-1
•Outputs sink 64mA (74F711A only)
FEATURES for 74F712A/74F712-1
•Consists of five 3-to-1 Multiplexers
•High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
•Designed for address multiplexing of dynamic RAM and other
applications
•30 termination impedance on each output – 74F712-1
•Outputs sink 64mA (74F712A only)
DESCRIPTION
The 74F711A/74F711-1 consist of five 2-to-1 multiplexers designed
for address multiplexing of dynamic RAMs and other multiplexing
applications. The 74F711A has a common select (S) input, an
Output Enable (OE
control the 3-State outputs. The outputs source 15mA and sink
64mA. The 74F711-1 is the same as the 74F711A except that is has
a 30 termination impedance on each output to reduce line noise
and the 3-State outputs sink 5mA.
When the inverting input (INV
inverted.
) input and an Output Inverting (INV) input to
) is Low, the input data path is
To improve speed and noise immunity, V
used.
The 74F712A/74F712-1 consist of five 3-to1 multiplexers designed
for address multiplexing of dynamic RAMs and other multiplexing
applications. The 74F712A has two select (S0, S1) inputs to
determine which set of five inputs will be propagated to the five
outputs. The outputs source 15mA and sink 64mA. The 74F712-1 is
the same as the 74F712A except that it has a 30 termination
impedance on each output to reduce line noise and the outputs sink
5mA.
TYPE
74F71 1A 6.0ns 30mA
74F71 1-1 6.5ns 29mA
74F712A 6.5ns 25mA
74F712-1 6.5ns 25mA
TYPICAL
PROPAGATION DELAY
and GND side pins are
CC
TYPICAL SUPPL Y
CURRENT
(TOTAL)
ORDERING INFORMATION
COMMERCIAL RANGE
DESCRIPTION
20-Pin Plastic DIP N74F71 1AN, N74F711-1N SOT146-1
24-Pin Plastic Slim
DIP (300 mil)
20-Pin Plastic SOL N74F71 1AD, N74F711-1D SOT163-1
24-Pin Plastic SOL N74F712AD, N74F712-1D SOT137-1
VCC = 5V ± 10%
T
= 0° C to +70°C
amb
N74F712AN, N74F712-1N SOT222-1
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
Dna, Dnb Data inputs 1.0/0.066 20µA/40µA
S Select input 1.0/0.033 20µA/20µA
74F711A/
74F711-1
74F712A/
74F712-1
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
1990 Dec 13 853-1368 01258
OE Output Enable input (active Low) 1.0/0.033 20µA/20µA
INV Output inverting input (active Low) 1.0/0.033 20µA/20µA
Q0 - Q4 Data outputs for 74F711A 750/106.7 15mA/64mA
Q0 - Q4 Data outputs for 74F711-1 750/8.33 15mA/5mA
Dna, Dnb, Dnc Data inputs 1.0/0.066 20µA/40µA
S0, S1 Select inputs 1.0/0.033 20µA/20µA
Q0 - Q4 Data outputs for 74F712A 750/106.7 15mA/64mA
Q0 - Q4 Data outputs for 74F712-1 750/8.33 15mA/5mA
2
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Philips Semiconductors Product specification
Multiplexers
PIN CONFIGURATION – 74F711A/74F711-1
1
D0a
2
D0b
3
Q0
4
Q1
5
GND
6
Q2
7
Q3
8
Q4
9
S
INV
LOGIC SYMBOL – 74F711A/74F711-1
D1a20
19
D1b
18
D2a
17
D2b
16
V
D3a
15
D3b
14
13
D4a
12
D4b
1110
OE
SF01215
CC
74F711A/74F71 1–1/
74F712A/74F712–1
PIN CONFIGURATION – 74F712A/74F712-1
1
S0
2
S1
3
Q0
4
Q1
5
Q2
6
GND
7
Q3
8
Q4
9
D0c
10
D1c
11
D2c
D3c
LOGIC SYMBOL – 74F712A/74F712-1
24
D0a
23
D1a
22
D2a
21
D3a
20
D4a
19
V
18
D0b
17
D1b
16
D2b
15
D3b
14
D4b
1312
D4c
SF01216
CC
1 2 20 19 18 17 15 14 13 12
10
11
= Pin 16
V
CC
GND = Pin 5
D0a D0b D1a D1b D2a D2b D3a
S
9
OE
INV
36
Q2 Q3
Q1Q0
47
D3b
D4a D4b
Q4
8
SF01217
LOGIC SYMBOL (IEEE/IEC) – 74F711A/74F711-1
1
11
10
1
2
20
19
18
17
15
14
13
12
G
EN1
M
MUX
1
3
4
6
7
8
24 18 9 23 17 10 22 16 11 21
D0a D0b D1a D1b D2a D2b D3a
D0c D1c D2c D3c
1
2S0S1
Q1Q0
35
47
VCC = Pin 19
GND = Pin 6
Q2 Q3
15 12 20 14 13
D4a D4b
D3b
Q4
8
SF01218
LOGIC SYMBOL (IEEE/IEC) – 74F712A/74F712-1
1
2
24
18
9
23
17
10
22
16
11
21
15
12
20
14
13
G1
G2
MUX
3
4
5
7
8
D4c
1990 Dec 13
SF01219
SF01220
3
Philips Semiconductors Product specification
Multiplexers
LOGIC DIAGRAM – 74F711A/74F711-1
11
OE
10
INV
9
S
1
D0a
2
D0b
20
D1a
19
D1b
18
D2a
17
D2b
15
D3a
14
D3b
74F711A/74F71 1–1/
74F712A/74F712–1
3
Q0
4
Q1
6
Q2
7
Q3
13
D4a
12
D4b
= Pin 16
V
CC
GND = Pin 5
FUNCTION TABLE – 74F711A/74F711-1
INPUTS OUTPUT
S INV OE Dna Dnb Qn
L L L Data a Data b Data a
H L L Data a Data b Data b
L H L Data a Data b Data a
H H L Data a Data b Data b
X X H X X Z
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “off” state
8
Q4
SF01221
1990 Dec 13
4
Philips Semiconductors Product specification
Multiplexers
LOGIC DIAGRAM – 74F712A/74F712-1
1
S0
2
S1
24
D0a
18
D0b
9
D0c
23
D1a
17
D1b
10
D1c
22
D2a
16
D2b
11
D2c
21
D3a
15
D3b
12
D3c
20
D4a
14
D4b
= Pin 19
V
CC
GND = Pin 6
D4c
13
74F711A/74F71 1–1/
74F712A/74F712–1
3
Q0
4
Q1
5
Q2
7
Q3
8
Q4
SF01222
FUNCTION TABLE – 74F712A/74F712-1
INPUTS OUTPUT
S0 S1 Dna Dnb Dnc Qn
L L Data a Data b Data c Data a
H L Data a Data b Data c Data b
X H Data a Data b Data c Data c
H = High voltage level
L = Low voltage level
X = Don’t care
1990 Dec 13
5
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