PANASONIC PV-DC3000 BLOCK DIAGRAM bl3 ccd

CCD C.B.A.		MAIN C.B.A.														CAMERA SIGNAL					DIGITAL C.B.A.
IC3001 (CCD)			IC3004 (CAMERA SIGNAL PROCESS)
																				P2001	AD0
		V1 1.44 Vp-p																		10
														AD0	2
																				P2001
																					AD1
														AD1
															3					11
														AD2	4					P2001	AD2
		0.5 V	50 µs																	12
														AD3
															5
CCD		Q3001											OUTPUT							P2001
														AD4	6						AD3
		P3001		DOUBLE						10BIT A/D			LATCH			10BIT DIGITAL DATA				15
IMAGE	10	BUFFER	26				AGC							AD5
SENSOR		9		SAMPLING HOLD						CONVERTER			CIRCUIT		7					P2001
																					AD4
														AD6						16
															8
			28																			10BIT DIGITAL DATA
																				P2001
														AD7
															9						AD5	TO RGB SIGNAL
																				13
														AD8
			29	DC OFFSET						TIMING					10							PROCESS BLOCK
																				P2001
				COMPENSATOR		SERIAL															AD6	DIAGRAM
										GENERATOR				AD9	11
																				14
						INTERFACE
																				P2001
																					AD7
																				17
				17	20	44	45	43		19	18	16
																				P2001
																					AD8
																				18
																				P2001	AD9
																				19
												IC3002 (TIMING PULSE GENERATOR)
												12	A/D CLOCK
												37 DOUBLE SAMPLING PULSE 1
												38 DOUBLE SAMPLING PULSE 2				V1 0.37 Vp-p		V1 3.74 Vp-p
												44	H CLEAR PULSE
												4	OB CLAMP PULSE			0.2 V	20 ns	2 V	10 ms
				IC3001 (V-DRIVE)
		P3001																V1 3.74 Vp-p
	5			14	DRIVE
		15							6			15	V1 PULSE
	6	P3001		16	DRIVE
		16
																		2 V	50 µs
		P3001
	4			12	DRIVE				10			16	V2 PULSE							P2001	CS (H)
		14
																				58
		P3001
	2			17	DRIVE															P2001	SERIAL DATA
		12							3			17	V3 PULSE		SERIAL DATA	10
																				51
		P3001
	3			19	DRIVE															P2001	SERIAL CLOCK
		13													SERIAL CLOCK	9
																				50
		P3001
	1			13	DRIVE				9			19	V4 PULSE							P2001
		11													TIMING GENERATOR CS (L)	11					TIMING GENERATOR CS (L)
																				57
		P3001
	16			20	DRIVE				2			24	SUB CONTROL PULSE							P2001
		4														1					MCLK
															2 FCK					9
			D3001
									8			20	V1A CHARGE PULSE							P2001
																6					CCD VD PULSE
															CCD VD PULSE					22
			+15V
									7			21	V1B CHARGE PULSE							P2001
																5					CCD HD PULSE
															CCD HD PULSE					21
									5			22	V3A CHARGE PULSE			48				P2001	SYSTEM CLOCK
															SYSTEM CLOCK					24
									4			23	V3B CHARGE PULSE			45				P2001	RESET(L)
															RESET(L)					76
																				P2001	2 FCK
																IC3003				8
	12	P3001										34	RESET PULSE			(INVERTER)
		7
	14															7	1
		P3001														6	2
	19											31	H1 PULSE
		6														5	3
	13															X3001
		P3001
	20											28	H2 PULSE			49.5MHz
		2
	17	P3001
		3				NOT USED
			Q3001									13	V-SUB CONTROL		NTSC/PAL SELECT	2		(FROM IC2001(8))		FROM SYSTEM
																		NTSC/PAL SELSCT		CONTROL BLOCK
																		CONTROL		DIAGRAM
						(FROM IC2003(4)) FROM SYSTEM CONTROL
						V-SUB CONTROL			BLOCK DIAGRAM