Panasonic MN89302 Datasheet
For Information Equipment
MN89302
SVGA Display Controller
Overview
The MN89302 is an LCD/CRT display controller with
IBM™ VGA-compatible registers. It features all the necessary interfaces for a compact display system: ISA bus interface, local bus interface, DRAM interface, and LCD panel
interface. The built-in graphics acceleration functions include
support for bit-block transfers (BITBLT) and hardware cursor.
Note: IBM™ and VGA are registered trademarks of International
Business Machines Corporation.
Features
Monochrome STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
32-monochrome gradation
Color STN LCD panel support
Maximum display size: 800 × 600
Support for single and dual panels
32-gradation for each color (RGB)
Color TFT LCD panel support
Maximum display size: 800 × 600
5-bit output for red and blue; 6-bit output for green
Maximum number of colors in concurrent display
320 × 240: 64k (TFT, STN)
640 × 480: 256/260K palette (TFT, STN)
800 × 600: 256/260K palette (TFT, STN)
Built-in graphics acceleration functions
• Bit-block transfers (BITBLT) to and from
host video memory and within video memory
• Hardware cursor (16 × 16 or 32 × 32)
Built-in automatic display centering
Built-in gradation control table (rewritable) for
optimizing gradation to match panel
DRAM interface with 16-bit bus
• Support for 2CAS/2WE mode
• Refresh control
Host interfaces
• ISA bus (16-bit)
• i386/i486 local bus (16-bit)
Note: i386 and i486 are trademarks of Intel Corporation.
Applications
Point-of-sale terminals, Factory automation terminals,
word processors, and other terminals
MN89302 For Information Equipment
Pin Assignment
ISA bus mode
VDDGND
LCAS
UCASWERAS
GND
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
VDDGND
UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
VDDGND
LD7
LD6
LD5
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
GND
V
DD
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
96959493929190898887868584838281807978777675747372717069686766
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
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65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LD4
LD3
LD2
LD1
LD0
V
DD
GND
DCLK
LP
FP
DISP
V
DD
GND
LOGICON
LCDON
BACKON
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
V
DD
SA0
GND
SD8
SD9
SD10
SD11
SD12
32
SA16
SA17
SA18
SA19
A20
A21
XIN
GND
GND
XOUT
TEST
RESET
MINTEST
SCANTEST
QFP128-P-1818
GND
MEMR
IOCS16
REFRESH
(TOP VIEW)
DD
SA1
V
MEMW
MEMCS16
IORD
IOWR
BIOSEN
IOCHRDY
AEN
GND
SBHE
SD15
SD14
SD13
For Information Equipment MN89302
Block Diagram
UD[7:0]
LD[7:0]
BACKON
LCDON
LOGICON
LP
FP
DISP
DCLK
XIN
RESET
TEST/MINTEST
Address[21:0]
SD[15:0]
AEN
SBHE
IOWR
IORD
SMEMW
SMEMR
IOCHRDY
REFRESH
MEMCS 16
IOCS 16
8
13
12/14
27
28
24
25
22
16
23
15
19
18
Gray scale
engine
49
50
51
56
55
54
57
LCD panel
controller
RAM table
LCD/CRT
Hardware
cursor
Attribute
control
Video FIFO
controller
Host
interface
BITBLT
Memory
write
buffer
Memory
interface
Access
attributer
Graphics
controller
91
93
94
92
26
MA[9:0]
MD[15:0]
RAS
UCAS
LCAS
WE
BIOSEN
MN89302 For Information Equipment
Pin Descriptions
Pin No. Symbol I/O Level Function Description
27 AEN I TTL Address Enable
"H" level input from this pin indicates that a DMA transfer is in
progress, so the chip does not respond to I/O access.
28 SBHE I TTL Byte High Enable
This input indicates the state of the 16-bit bus.
24 IOWR I TTL I/O Write
This input indicates an I/O write request.
25 IORD I TTL I/O Read
This input indicates an I/O read request.
22 SMEMW I TTL Memory Write
This input indicates a memory write request dedicated for an
address space in the first megabyte (000000 to 0FFFFFH).
16 SMEMR I TTL Memory Read
This input indicates a memory read request dedicated for an
address space in the first megabyte (000000 to 0FFFFFH).
6 to 5 A[21:20] I TTL Address[21:20]
These inputs give the address 21:20.
4 to 1, SA[19:0] I TTL Address[19:0]
128 to 115, These inputs give the address 19:0.
21 ,39
30 to 48 SD[15:0] I/O TTL Data[15:0]
These pins represent the host data bus.
23 IOCHRDY I/O TTL I/O Channel Ready
This pin is "L" level when I/O or memory access is given wait
states.
19 MEMCS16 O TTL Memory Chip Select 16
This output indicates to the system that 16-bit memory access is
available.
18 IOCS16 O TTL I/O Chip Select 16
This output indicates to the system that 16-bit I/O access is
available.
15 REFRESH I TTL Refresh
"L" level input indicates that the system is refreshing its DRAM.
89 to 80 MA[9:0] I/O CMOS Memory Address
These outputs give the address of the display memory .
91 RAS O CMOS Row Address Strobe (RAS).
This output is the strobe signal for the row address latch.
93 UCAS O CMOS Upper Column Address Strobe (UCAS)
This output is the strobe signal for the upper column address
latch. In the 2WE mode, however, it functions as the CAS
signal.
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