A/D, D/C Converters for Image Signal Processing
MN65761T
Low Power 9-Bit CMOS A/D Converter for Image Processing
Overview
The MN65761T is a high-speed 9-bit CMOS analog-
to-digital converter for image processing applications.
It uses a half flash structure based on chopper comparators and achieves both high speed and low power
consumption with multiplexing.
It provides separate power supply pins for the circuits
driving the low-voltage digital output pins.
Features
Maximum conversion rate: 18 MSPS (min.)
Linearity error: ±1.3 LSB (typ.)
Differential linearity error: ±0.6 LSB (typ.)
Power supply voltage: 3.6 V or 2.6 V
Power consumption: 60 mW (typ.) (f
=18 MHz)
CLK
Applications
Digital television receivers
Digital video equipment
Digital image processing equipment
Pin Assignment
N.C.
N.C.D6D5D4DV
N.C.
N.C.
D7
D8
N.C.
AV
AV
CLK
NOE
POWD
N.C.
N.C.
SS
DD
3635343332313029282726
37
38
39
40
41
42
43
44
45
46
47
48
1234567891011
N.C.
N.C.
TQFP048-P-0707
DDLAVSS
SS
SS
RT
DD
RTS
V
V
AV
AV
AV
(TOP VIEW)
D3D2D1
DD
RM
V
V
AV
N.C.
N.C.
25
N.C.
24
N.C.
23
D0
22
TEST
21
AV
20
19
18
17
16
15
14
13
12
IN
N.C.
N.C.
AV
AV
V
RBS
V
RB
AV
N.C.
N.C.
DD
DD
SS
SS
1
MN65761T A/D, D/C Converters for Image Signal Processing
Block Diagram
SS
AVDDAVDDAV
20
191817
RBSVRB
V
16
15
31
Upper comparator (5 bits)
31
Upper encoder (5 bits)
SS
RM
IN
AVSSAVDDAVDDAV
10
V
V
9
8
7
6
Clock generator
5
VRTV
5
31
31
SS
RTS
AV
4
3
31
Lower comparator A (4 bits)
Lower encoder A (4 bits)
Lower comparator B (4 bits)
Lower encoder B (4 bits)
31
55
Error
correction
and
data latch
21
22
27
28
29
TEST
(LSB)
D0
D1
D2
303132
D3
AV
SS
D4D5D6
DDL
DV
33
343940
D7
D8
42
43
44
45
46
SS
DD
CLK
AV
NOE
POWD
AV
2
A/D, D/C Converters for Image Signal Processing MN65761T
Pin Descriptions
Pin No. Symbol Function Description
1 N.C. No connection
2 N.C. No connection
3AVSSGround for analog circuits
4V
RTS
5VRTReference voltage input (TOP)
6AVSSGround for analog circuits
7AVDDPower supply for analog circuits
8VRMIntermediate reference voltage
9AVDDPower supply for analog circuits
10 V
IN
11 N.C. No connection
12 N.C. No connection
13 N.C. No connection
14 N.C. No connection
15 AV
16 V
17 V
18 AV
19 AV
20 AV
SS
RB
RBS
SS
DD
DD
21 TEST Test mode selection
22 D0 Digital code output (LSB)
23 N.C. No connection
24 N.C. No connection
25 N.C. No connection
26 N.C. No connection
27 D1 Digital output
28 D2 Digital output
29 D3 Digital output
30 AV
31 DV
SS
DDL
32 D4 Digital output
33 D5 Digital output
34 D6 Digital output
35 N.C. No connection
36 N.C. No connection
37 N.C. No connection
38 N.C. No connection
39 D7 Digital output
40 D8 Digital output (MSB)
Reference voltage power supply (TOP)
Analog signal input
Ground for analog circuits
Reference voltage input (BOTTOM)
Reference voltage power supply (BOTTOM)
Ground for analog circuits
Power supply for analog circuits
Power supply for analog circuits
Ground for analog circuits
Power supply for low-voltage digital outputs
3
MN65761T A/D, D/C Converters for Image Signal Processing
Pin Descriptions (continued)
Pin No. Symbol Function Description
41 N.C. No connection
42 AV
43 AV
SS
DD
44 CLK Sampling clock
45 NOE Digital output enable
46 POWD Power down mode selection
47 N.C. No connection
48 N.C. No connection
Absolute Maximum Ratings Ta=25˚C
Parameter Symbol Rating Unit
Power supply voltage V
Power supply voltage for digital output circuits DV
Input voltage V
Output voltage V
Operating ambient temperature T
Storage temperature T
Recommended Operating Conditions
Parameter Symbol min typ max Unit
Power supply voltage V
Power supply voltage for digital output circuits DV
Digital input "H" level V
voltage "L" level V
Reference "H" level V
voltage "L" level V
Clock "H" level pulse width t
Analog input voltage V
Electrical Characteristics V
Parameter Symbol Conditions min typ max Unit
Power consumption P
Resolution RES VDD=3.5V, DV
Linearity error E
Differential linearity error E
Maximum conversion rate F
Clock frequency f
Analog input dynamic range D
Output "H" level I
current "L" level I
Output delay time t
Analog input capacitance C
Ground for analog circuits
Power supply for analog circuits
"L" level pulse width t
=AVDD=3.6V, DV
DD
f
C
=18 MSPS
CLK
(not including reference current)
f
L
D
=18MSPS, VDD=3.5V ±1.3 ±2.5 LSB
CLK
VRT=3.3V, DV
VRB=1.3V, CLK
C(max.)VDD
CLK
R
OH
OL
d
I
=3.5V, DV
VDD=3.5V, DV
VDD=3.5V, DV
VOH=DV
VOL=0.4V 1.5 mA
T a=70˚C, CL=100Ω+10pF 10 20 35 ns
V
pin 26 pF
IN
DD
DDL
I
O
opr
stg
VDD=AVDD=3.6V, DV
DD
DDL
IH
IL
RT
RB
WH
WL
AIN
3.15 3.60 3.70 V
2.50 2.60 3.70 V
AV
DD
AV
AV
25 ns
25 ns
AV
=2.6V , AVSS=0V, T a=25˚C
DDL
× 0.55 AV
SS
SS
SS
– 0.3 to +7.0 V
– 0.3 to V
– 0.3 to V
– 0.3 to V
+0.3 V
DD
+0.3 V
DD
+0.3 V
DD
–20 to +70 ˚C
–55 to +125 ˚C
=2.6V, VSS=AVSS=0V, Ta=25˚C
DDL
AV
× 0.20 V
DD
3.30 AV
1.30 V
AV
DD
DD
DD
60 100 mW
=2.5V 9 bit
DDL
=2.5V
DDL
=50±5%
Duty
=2.5V 18 MSPS
DDL
=2.5V 1 18 MHz
DDL
=2.5V 2 V
DDL
– 0.8V –1.5 mA
DDL
±0.6 ±1.0 LSB
RT –VRB
V
V
V
V
4
A/D, D/C Converters for Image Signal Processing MN65761T
Timing Chart
The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital
output 2.5 clock cycles later at the rising edge of the clock signal.
t
WHtWL
Clock
Analog input
Data output
Note: The circles indicate analog signal sampling points.
N
N+1
N+2
N+3
N–3 N–2 N–1 N+1N
(20ns)
t
d
N+4
5
MN65761T A/D, D/C Converters for Image Signal Processing
Package Dimensions (Unit:mm)
TQFP048-P-0707
9.00±0.20
7.00±0.10
2536
37
48
(0.75)
0.10
0.50
121
+0.10
-
0.05
0.20
SEATING PLANE
24
13
(0.75)
(1.00)
1.20max.
0.10±0.10
7.00±0.10
0.05
-
+0.10
0.125
9.00±0.20
(1.00)
0 to 10°
0.50±0.10
6
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