Panasonic MN3304 User Manual

MN3300 Series

MN3304

512-Stage Ultra Low Voltage Operation BBD for Audio Signals

■ Overview

■ Pin Assignment

The MN3304 is a 512-stage ultra low voltage operation BBD variable
delay line in audio frequency range. The device operates on +3V
supply and provides a signal delay up to 25.6 ms and is suitable for
use as reverberation effect of low voltage operation audio equipment
such as portable stereo, radio cassette recorder and microphone.

■ Features

•

Variable signal delay of the audio signal : 0.256 to 25.6 ms

•

Wide range of supply voltage : 1.8 to 5.0 V

•

No insertion loss : L

•

Wide dynamic range : S/N=73 dB typ.

•

Low distortion : THD=0.7 % typ. (V

•

Clock frequency range :10 to 200 kHz (1.8 V≤V

•

N-channel 2-layer silicon gate process

•

8-Pin Dual-In-Line Plastic Package

=0 dB typ.

i

=0.22 V

i

10 kHz to 1 MHz (4.0 V≤V

rms

)

DD

<4.0 V)

DD

≤5.0 V)

GND

CP2

IN

V

DD

1

2

MN3304

3

4

DIP008-P-0300

V

8

OUT

7

CP1

6

V

5

■ Block Diagram

■ Applications

•

Reverberation and echo effects of audio equipment such as radio
cassette recorder, car radio, portable radio, portable stereo, echo
microphone and Karaoke machine, etc.

•

Sound effect of electronic musical instruments

•

Variable or fixed delay of analog signals

IN

3

CP1

6

512-Stage

BBD

4

DD

V

CP2

2

1

GND

8

V

7

OUT

5

V

■ Pin Descriptions

Pin No.

Symbol Pin Name Description

1 GND Ground pin Connected to ground.
2 CP2 Clock input 2 Basic clock pulse is applied to transfer electric charge of BBD.
3 IN Signal input pin Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin.
4VDDVDD apply pin Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse

input gate of the BBD transfer gate.

Furthermore, voltage is supplied to step-up circuit.
5VD1VD1 apply pin The same phase clock pulse as CP1 is applied through capacitor.
6 CP1 Clock input 1 Clock pulse of inverted phase to CP2 is applied.
7 OUT Output pin Composed signal of 1024th and 1025th stages is output.
8VD2VD2 apply pin The same phase clock pulse as CP2 is applied through capacitor.

D2

D1

D2

D1

1

MN3304 MN3300 Series

■ Absolute Maximum Ratings Ta=25°C

Parameter Symbol Ratings Unit

Pin voltage VDD, VD1, VD2, VCP, V
Output voltage V
Operating ambient temperature T
Storage temperature T

O

opr

stg

■ Operating Conditions Ta=25°C

Parameter Symbol Conditions min typ max Unit

Supply voltage V
Clock voltage "H"level V
Clock voltage "L"level V
Clock input capacitance C
Clock frequency f
Clock pulse width t
Clock rise time t
Clock fall time t
Clock cross point V

Note) *1: ( ) : VDD=4.0 to 5.0 V

*2:T=1/fCP (Clock period)

CPH

CPL

CP

w(CP)

r(CP)

f(CP)

DD

CP

3

*

3

*

3

*

3

*

X

*3: Clock pulse waveforms

I

− 0.3 to +6.0 V

− 0.3 to +6.0 V

−20 to +60 °C

−55 to +125 °C

+1.8 +3.0 +5.0 V

V

DD

0V

10

0 0.3V

t

CP2

CP1

r(CP)

90%
50%

10%

t

w(CP)

T

400 pF

200(1000)

0.5T
500 ns
500 ns

CPH

t

f(CP)

V

1

*

kHz

2

*

V

3V

V

X

■ Electrical Characteristics VDD=V

CPH

=3V, V

=0V, RL=56kΩ, LPF : fC=20kHz, Att=48dB/oct., Ta=25°C

CPL

Parameter Symbol Conditions min typ max Unit

Supply current I
Signal delay time 1 t
Signal delay time 2 t
Input signal frequency f

DDfCP

D1

D2

i

=40 kHz 0.05 mA

VDD=1.8 to 4.0 V, fCP=10 to 200 kHz N
VDD=4.0 to 5.0 V, fCP=10 kHz to 1 MHz 2·f
fCP=40 kHz, Vi=0.22 V

rms

12 kHz

*

CP

Output attenuation≤3 dB(0 dB at fi=1 kHz)

Input signal amplitude υ
Insertion loss L
Total harmonic distortion THD fCP=40 kHz, fi=1 kHz, Vi=0.22 V
Output noise voltage V

fCP=40 kHz, fi=1 kHz, THD=2.5 % 0.32 0.5 V

i

fCP=40 kHz, fi=1 kHz, Vi=0.22 V

i

nofCP

=100 kHz, Weighted by "A"curve 0.098 0.2 mV

rms

rms

−40 4 dB

0.7 2.5 %

Signal to noise ratio S/N 73 dB

Note) * : N=BBD stages

■ Circuit Diagram

8V

513512321

7 OUT

5V

GND

V
CP1
CP2

3IN

1
4

DD

6
2

ms

rms

rms

D2

D1

2