Panasonic MN3304 User Manual

MN3300 Series

MN3304

512-Stage Ultra Low Voltage Operation BBD for Audio Signals

■ Overview

■ Pin Assignment

The MN3304 is a 512-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on +3V supply and provides a signal delay up to 25.6 ms and is suitable for use as reverberation effect of low voltage operation audio equipment such as portable stereo, radio cassette recorder and microphone.

■ Features

∙Variable signal delay of the audio signal : 0.256 to 25.6 ms

∙Wide range of supply voltage : 1.8 to 5.0 V

∙No insertion loss : Li=0 dB typ.

∙Wide dynamic range : S/N=73 dB typ.

∙Low distortion : THD=0.7 % typ. (Vi=0.22 Vrms)

∙Clock frequency range : 10 to 200 kHz (1.8 V≤VDD<4.0 V)

10 kHz to 1 MHz (4.0 V≤VDD≤5.0 V)

∙N-channel 2-layer silicon gate process

∙8-Pin Dual-In-Line Plastic Package

■ Applications

∙Reverberation and echo effects of audio equipment such as radio cassette recorder, car radio, portable radio, portable stereo, echo microphone and Karaoke machine, etc.

∙Sound effect of electronic musical instruments

∙Variable or fixed delay of analog signals

GND		1	8			VD2
CP2		2	7			OUT
			MN3304
IN		3	6			CP1
VDD		4	5			VD1

DIP008-P-0300

■ Block Diagram

		CP1	CP2
		6	2	8
					VD2
IN	3	512-Stage		7	OUT
		BBD		5
					VD1
		4	1
		DD	GND
		V

■ Pin Descriptions

Pin No.	Symbol	Pin Name	Description
1	GND	Ground pin	Connected to ground.
2	CP2	Clock input 2	Basic clock pulse is applied to transfer electric charge of BBD.
3	IN	Signal input pin	Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin.
4	VDD	VDD apply pin	Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse
			input gate of the BBD transfer gate.
			Furthermore, voltage is supplied to step-up circuit.
5	VD1	VD1 apply pin	The same phase clock pulse as CP1 is applied through capacitor.
6	CP1	Clock input 1	Clock pulse of inverted phase to CP2 is applied.
7	OUT	Output pin	Composed signal of 1024th and 1025th stages is output.
8	VD2	VD2 apply pin	The same phase clock pulse as CP2 is applied through capacitor.

1

MN3304

MN3300 Series

■ Absolute Maximum Ratings Ta=25°C

Parameter

Symbol

Ratings

Unit

Pin voltage

VDD, VD1, VD2, VCP, VI

− 0.3 to +6.0

V

Output voltage

VO

− 0.3 to +6.0

V

Operating ambient temperature

Topr

−20 to +60

°C

Storage temperature

Tstg

−55 to +125

°C

■ Operating Conditions Ta=25°C

Parameter

Symbol

Conditions

min

typ

max

Unit

Supply voltage

VDD

+1.8

+3.0

+5.0

V

Clock voltage "H"level

VCPH

VDD

V

Clock voltage "L"level

VCPL

0

V

Clock input capacitance

CCP

400

pF

Clock frequency

f

CP

10

200(1000)*1

kHz

Clock pulse width

t

*3

0.5T*2

w(CP)

Clock rise time

*3

500

ns

tr(CP)

Clock fall time

*3

500

ns

tf(CP)

Clock cross point

V

*3

0

0.3V

V

X

CPH

Note) *1 : ( ) : VDD=4.0 to 5.0 V

*3 : Clock pulse waveforms

tr(CP)

tf(CP)

*2 : T=1/fCP (Clock period)

CP2

3V

90%

CP1

50%

10%

tw(CP)

V

X

T

■ Electrical Characteristics VDD=VCPH=3V, VCPL=0V, RL=56kΩ, LPF : fC=20kHz, Att=48dB/oct., Ta=25°C

Parameter

Symbol

Conditions

min

typ

max

Unit

Supply current

IDD

fCP=40 kHz

0.05

mA

Signal delay time 1

tD1

VDD=1.8 to 4.0 V, fCP=10 to 200 kHz

N *

ms

Signal delay time 2

tD2

VDD=4.0 to 5.0 V, fCP=10 kHz to 1 MHz

2·fCP

Input signal frequency

fi

fCP=40 kHz, Vi=0.22 Vrms

12

kHz

Output attenuation≤3 dB(0 dB at fi=1 kHz)

Input signal amplitude

υi

fCP=40 kHz, fi=1 kHz, THD=2.5 %

0.32

0.5

Vrms

Insertion loss

Li

fCP=40 kHz, fi=1 kHz, Vi=0.22 Vrms

−4

0

4

dB

Total harmonic distortion

THD

fCP=40 kHz, fi=1 kHz, Vi=0.22 Vrms

0.7

2.5

%

Output noise voltage

Vno

fCP=100 kHz, Weighted by "A"curve

0.098

0.2

mVrms

Signal to noise ratio

S/N

73

dB

Note) * : N=BBD stages

■ Circuit Diagram

							8	VD2
IN	3	1	2	3	512	513	7	OUT
GND 1
VDD	4						5	VD1
CP1	6
CP2	2

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