ON Semiconductor NTP75N03L09, NTB75N03L09 Technical data

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NTP75N03L09, NTB75N03L09
Power MOSFET
75 Amps, 30 Volts, N−Channel TO−220 and D
This Logic Level Vertical Power MOSFET is a general purpose part that provides the “best of design” available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The drain−to−source diode has a ideal fast but soft recovery.
Features
Pb−Free Packages are Available
Ultra−Low R
SPICE Parameters Available
Diode is Characterized for Use in Bridge Circuits
I
and V
DSS
High Avalanche Energy Specified
ESD JEDAC Rated HBM Class 1, MM Class B, CDM Class 0
T ypical Applications
Power Supplies
Inductive Loads
PWM Motor Controls
Replaces MTP75N03HDL and MTB75N03HDL in Many
Applications
DS(on)
2
PAK
, Single Base, Advanced Technology
DS(on)
Specified at Elevated Temperatures
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75 AMPERES, 30 VOLTS
= 8 m
N−Channel
D
S
TO−220
CASE 221A
STYLE 5
MARKING
DIAGRAMS
4
Drain
75N
03L09
AYWW
G
4
R
DS(on)
Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 6
1
2
3
4
2
D
PAK
2
1
3
75N03L09 = Device Code A = Assembly Location Y = Year WW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
1 Publication Order Number:
CASE 418AA
STYLE 2
1
Gate
75N03L09
1
Gate
NTP75N03L09/D
2
Drain
4
Drain
AYWW
2
Drain
3 Source
3 Source
NTP75N03L09, NTB75N03L09
MAXIMUM RATINGS (T
Drain−to−Source Voltage V Drain−to−Gate Voltage
= 25°C unless otherwise noted)
J
Rating
Symbol Value Unit
30 Vdc 30 Vdc
V
DSS DGB
(RGS = 10 M) Gate−to−Source Voltage − Continuous V Non−repetitive (tp 10 ms) V
GS GS
±20 Vdc ±24 Vdc
Drain Current
I
I I
DM
P
D D
D
− Continuous @ T
− Continuous @ T
= 25°C
C
= 100°C
C
− Single Pulse (tp 10 s)
Total Power Dissipation @ TC = 25°C
Derate above 25°C Total Power Dissipation @ T
= 25°C (Note 1)
A
Operating and Storage Temperature Range TJ and T Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C
= 38 Vdc, VGS = 10 Vdc, L = 1 mH, IL(pk) = 55 A, VDS = 40 Vdc)
(V
DD
E
AS
stg
75
Adc
59
225 125
1.0
2.5
Apk
W
W/°C
W
−55 to 150 °C 1500 mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
R R R
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds T
JC
JA
JA
L
1.0
°C/W
62.5 50
260 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended pad size.
ORDERING INFORMATION
Device Package Shipping
NTP75N03L09 TO−220 50 Units/Rail NTP75N03L09G TO−220
50 Units/Rail
(Pb−Free) NTB75N03L09 D2PAK 50 Units/Rail NTB75N03L09G D2PAK
50 Units/Rail
(Pb−Free) NTB75N03L09T4 D2PAK 800 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTP75N03L09, NTB75N03L09
f 1.0 MHz)
V
DD
Vdc, I
D
Adc,
V
DS
Vdc) (Note 2)
dlS/dt 100 A/s) (Note 2)
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage (Note 2)
(V
= 0 Vdc, ID = 250 Adc)
GS
V
(BR)DSS
Temperature Coefficient (Negative) Zero Gate Voltage Drain Current
(V
= 30 Vdc, VGS = 0 Vdc)
DS
(V
= 30 Vdc, VGS = 0 Vdc, TJ = 150°C)
DS
Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
(V
= VGS, ID = 250 Adc)
DS
V
Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 2)
(V
= 5.0 Vdc, ID = 37.5 Adc)
GS
Static Drain−to−Source On Resistance (Note 2)
(V
= 10 Vdc, ID = 75 Adc)
GS
= 10 Vdc, ID = 37.5 Adc, TJ = 125°C)
(V
GS
R
V
Forward Transconductance (Notes 2 & 4) (VDS = 3 Vdc, ID = 20 Adc) g
DYNAMIC CHARACTERISTICS (Note 4)
Input Capacitance Output Capacitance
(VDS = 25 Vdc, VGS = 0,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time Rise Time Turn−Off Delay Time
(VGS = 5.0 Vdc,
V
= 20 Vdc, ID = 75 Adc,
20
DD
RG = 4.7 ) (Note 2)
75
Fall Time t Gate Charge (VGS = 5.0 Vdc,
ID = 75 Adc,
V
= 24 Vdc) (Note 2)
24
DS
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (IS = 75 Adc, VGS = 0 Vdc)
(I
= 75 Adc, VGS = 0 Vdc, TJ = 125°C)
S
(Note 2)
I
DSS
GSS
GS(th)
DS(on)
DS(on)
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
f
Q
T
Q
1
Q
2
V
SD
30 34
−57
Vdc
mV°C
Adc
1.0 10
±100 nAdc
1.0
1.6
−6
2.0
Vdc
mV°C
m
6.5 8.0 Vdc
0.52
0.35
0.68
0.50
58 m
4398 5635
1160 1894
317 430
16 30
130 200
65 110
105 175
57 75
nC
11 15
34 50
1.19
1.09
1.25
Vdc
pF
ns
Reverse Recovery Time (Note 4) (IS = 75 Adc, VGS = 0 Vdc
dl
/dt = 100 A/s) (Note 2)
S
Reverse Recovery Stored Charge (Note 4)
2. Pulse Test: Pulse Width  300 S, Duty Cycle 2%.
3. Switching characteristics are independent of operating junction temperatures.
4. From characterization test data.
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t
rr
t
a
t
b
Q
RR
37
20
17
0.023
ns
C
3
NTP75N03L09, NTB75N03L09
120
90
60
30
, DRAIN CURRENT (AMPS)
D
I
TJ = 25°C
0
0
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
0.40.2 , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
DS
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.0085
0.008
0.0075
0.007
0.0065
0.006
0.0055
0.005
, DRAIN−TO SOURCE RESISTANCE ()
0.0045
0.004
DS(on)
R
VGS = 5 V
20 60 70 120
10
ID, DRAIN CURRENT (AMPS)
VGS = 4 V
VGS = 4.5 V
VGS = 5 V
VGS = 6 V VGS = 8 V VGS = 10 V
TJ = 100°C
TJ = 25°C
TJ = −55°C
504030
VGS = 3.5 V
VGS = 3 V
VGS = 2.5 V
80 90 100
150
VDS 10 V
135
120
105
90 75 60 45 30
, DRAIN CURRENT (AMPS)
D
I
15
0
2.6
0.5 2.5 321.5 3.514
0.009 TJ = 25°C
0.008
0.007
0.006
0.005
, DRAIN−TO SOURCE RESISTANCE ()
0.004
DS(on)
0806040 10020 120
R
TJ = 25°C
TJ = 100°C
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
TJ = −55°C
VGS = 5 V
VGS = 10 V
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Drain Current and
Temperature
1.6
1.4
1.2
1
0.8
0.6
−50 50250−25 75 125 150
, DRAIN−TO SOURCE RESISTANCE (NORMALIZED)
DS(on)
Figure 5. On−Resistance Variation Temperature
R
V
= 5.0 V
GS
I
= 37.5 A
D
TJ, JUNCTION TEMPERATURE (°C)
100
1000
100
10
, LEAKAGE (nA)
DSS
I
1
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4
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS = 0 V
TJ = 125°C
TJ = 100°C
515202510 30
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current vs.
Voltage
NTP75N03L09, NTB75N03L09
12000
10000
8000
6000
4000
C, CAPACITANCE (pF)
2000
0
10
1000
100
t, TIME (ns)
10
1
V
V
GS
DS
C
iss
C
oss
C
rss
4 2 0 2 4 6 8 10121416182022
68
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VDS = 0 V V
= 0 V
GS
T
= 25°C
J
25
8
V
6
Q
4
1
DS
Q
T
Q
2
2
, GATE−TO−SOURCE VOLTAGE (V)
GS
0
V
0102030405060
Q
3
Qg, TOTAL GATE CHARGE (nC)
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
t
r
t
f
t
d(off)
t
d(on)
9.16.24.7
VDD = 15 V V
GS
TJ = 25°C I
= 75 A
D
2.2 10 20 RG, GATE RESISTANCE ()
= 5 V
75 70 65 60 55 50 45 40 35 30
25 20
, SOURCE CURRENT (AMPS)
15
S
I
10
VGS = 0 V T
= 25°C
J
5 0
0.0 0.80.60.40.2 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
V
GS
ID = 75 A T
= 25°C
J
30
20
10
0
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1600 1400 1200 1000
800 600 400
AVALANCHE ENERGY (mJ)
200
, SINGLE PULSE DRAIN−TO−SOURCE
AS
0
E
25 7550 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Avalanche Energy vs.
Starting Junction Temperature
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Figure 10. Diode Forward Voltage vs. Current
ID = 75 A
5
NTP75N03L09, NTB75N03L09
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
SEATING
−T−
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED.
DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
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6
NTP75N03L09, NTB75N03L09
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
−T−
SEATING PLANE
−B−
G
C
E
V
4
W
A
231
S
K
W
J
D
3 PL
M
0.13 (0.005) T
M
B
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65 B 0.380 0.405 9.65 10.29 C 0.160 0.190 4.06 4.83 D 0.020 0.036 0.51 0.92 E 0.045 0.055 1.14 1.40
F 0.310 −−− 7.87 −−−
G 0.100 BSC 2.54 BSC
J 0.018 0.025 0.46 0.64 K 0.090 0.110 2.29 2.79 M 0.280 −−− 7.11 −−− S 0.575 0.625 14.60 15.88 V 0.045 0.055 1.14 1.40
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
SOLDERING FOOTPRINT*
8.38
0.33
10.66
0.42
1.016
0.04
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
inches
mm
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTP75N03L09, NTB75N03L09
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTP75N03L09/D
8
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