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NTP60N06L, NTB60N06L
Power MOSFET
60 Amps, 60 Volts,
Logic Level
N−Channel TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters, power motor controls and bridge circuits.
Features
• Pb−Free Packages are Available
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
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60 AMPERES, 60 VOLTS
R
DS(on)
G
= 16 mW
N−Channel
D
S
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 75 Vdc, VGS = 5.0 Vdc,
L = 0.3 mH, IL(pk) = 55 A,VDS = 60 Vdc)
Thermal Resistance,
− Junction−to−Case
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
= 25°C unless otherwise noted)
C
Rating Symbol Value Unit
stg
60 Vdc
60 Vdc
"15
"20
60
42.3
180
150
1.0
2.4
− 55 to
175
454 mJ
1.0
62.5
260 °C
Vdc
Adc
Apk
W
W/°C
W
°C
°C/W
V
V
V
E
R
R
DSS
DGR
GS
GS
I
I
I
DM
P
AS
q
q
T
D
D
D
JC
JA
L
4
4
1
2
TO−220AB
1
2
CASE 221A
STYLE 5
3
3
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
NTx60N06LG
AYWW
1
Gate
Drain
NTx60N06L = Device Code
x = B or P
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
3
Source
2
Gate
Drain
NTx
60N06LG
AYWW
1
Drain
4
3
2
Source
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 3
1 Publication Order Number:
NTP60N06L/D
NTP60N06L, NTB60N06L
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
C
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
(V
= 0 Vdc, ID = 250 mAdc)
GS
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ =150°C)
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 2)
(VGS = 5.0 Vdc, ID = 30 Adc)
Static Drain−to−Source On−Voltage (Note 2)
(VGS = 5.0 Vdc, ID = 60 Adc)
(VGS = 5.0 Vdc, ID = 30 Adc, TJ = 150°C)
Forward Transconductance (Note 2) (VDS = 8.0 Vdc, ID = 12 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance C
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
(V
= 48 Vdc, ID = 60 Adc,
Rise Time t
Turn−Off Delay Time t
DD
VGS = 5.0 Vdc,
RG = 9.1 W) (Note 2)
Fall Time t
Gate Charge
(VDS = 48 Vdc, ID = 60 Adc,
VGS = 5.0 Vdc) (Note 2)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (IS = 60 Adc, VGS = 0 Vdc) (Note 2)
(IS = 60 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 60 Adc, VGS = 0 Vdc,
dlS/dt = 100 A/ms) (Note 2)
Reverse Recovery Stored Charge Q
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
C
C
t
d(on)
d(off)
Q
Q
Q
V
FS
iss
oss
rss
SD
t
rr
t
a
t
b
RR
60
−
72.8
75.2
−
−
mV/°C
mAdc
Vdc
−
−
−
−
1.0
10
− − ± 100 nAdc
Vdc
1.0
−
1.58
5.4
2.0
−
mV/°C
mW
− 12.4 16
Vdc
−
−
0.793
0.861
1.17
−
− 48 − mhos
− 2195 3075 pF
− 675 945
− 188 380
− 50.4 100 ns
r
− 576 1160
− 100 200
f
T
1
2
− 237 480
− 43.2 65 nC
− 6.4 −
− 29 −
−
−
− 81.9 −
0.98
0.86
1.05
−
Vdc
ns
− 42.1 −
− 39.8 −
− 0.172 −
mC
ORDERING INFORMATION
Device Package Shipping
NTP60N06L TO−220AB 50 Units / Rail
NTP60N06LG TO−220AB
50 Units / Rail
(Pb−Free)
NTB60N06L
NTB60N06LG
D2PAK
D2PAK
50 Units / Rail
50 Units / Rail
(Pb−Free)
NTB60N06LT4
NTB60N06LT4G
D2PAK
D2PAK
800 Units / Tape & Reel
800 Units / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
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2
NTP60N06L, NTB60N06L
0
120
120
I
, DRAIN CURRENT (AMPS)
R
, DRAIN−TO−SOURCE RESISTANCE (
)
R
DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
0
100
6 V
5 V
80
60
40
20
D
W
0.03
0.026
0.022
0.018
0.014
0.01
0.006
DS(on)
0
8 V
VGS = 10 V
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
VGS = 5 V
TJ = 100°C
TJ = 25°C
TJ = −55°C
40200
ID, DRAIN CURRENT (AMPS)
80 100
4.5 V
4 V
3.5 V
3 V
VDS ≥ 10 V
100
80
60
40
, DRAIN CURRENT (AMPS)
20
D
I
53210
0.03
0.026
0.022
0.018
0.014
0.01
, DRAIN−TO−SOURCE RESISTANCE (W)
0.006
12060
DS(on)
R
0
0
TJ = 100°C
VDS = 5 V
VGS = 10 V
TJ = 25°C
TJ = −55°C
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
TJ = 100°C
TJ = 25°C
TJ = −55°C
40200
ID, DRAIN CURRENT (AMPS)
60
80 100
64321
12
Figure 3. On−Resistance versus Gate−to−Source
Voltage
2
ID = 30 A
VGS = 5 V
1.8
1.6
1.4
1.2
1
0.8
0.6
TJ, JUNCTION TEMPERATURE (°C)
DS(on),
Figure 5. On−Resistance Variation with
Temperature
10,000
1000
, LEAKAGE (nA)
100
DSS
I
150
1751251007550250−25−50
10
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3
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
TJ = 150°C
TJ = 125°C
TJ = 100°C
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
20 6
30 40 50
Figure 6. Drain−to−Source Leakage Current
versus Voltage
NTP60N06L, NTB60N06L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
8000
6000
C
iss
4000
C
rss
2000
C, CAPACITANCE (pF)
0
10
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
5
V
GS
Figure 7. Capacitance Variation
VGS = 0 VVDS = 0 V
0 5 10 15 2520
V
DS
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4
TJ = 25°C
C
iss
C
oss
C
rss
NTP60N06L, NTB60N06L
6
Q
T
Q
2
20 5040
ID = 60 A
TJ = 25°C
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V
5
Q
1
4
3
2
1
0
0
10 30
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
60
VGS = 0 V
TJ = 25°C
50
40
1000
t
r
V
GS
100
t, TIME (ns)
10
1 10 100
t
f
t
d(off)
t
d(on)
RG, GATE RESISTANCE (W)
VDS = 30 V
ID = 60 A
VGS = 5 V
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
30
20
10
, SOURCE CURRENT (AMPS)
S
I
0
0.38 0.46 0.54 0.62 0.7 0.78
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (V
) is exceeded and the
DSS
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− TC)/(R
qJC
).
TJ = 150°C
TJ = 25°C
0.860.3
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance w i th i ndust ry c us tom.
The energy rating must b e derated for temperature as shown
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5
NTP60N06L, NTB60N06L
5
I
, DRAIN CURRENT (AMPS)
in the accompanying graph (F igure 12). M aximum ener gy at current s below rated continuous I
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10
D
1
0.1 1
Figure 11. Maximum Rated Forward Biased
1.0
SAFE OPERATING AREA
10 ms
100 ms
1 ms
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Safe Operating Area
D = 0.5
10 ms
dc
10
100
equal the values indicated.
500
400
300
200
100
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
0
0
AS
25 50 75 100 125
E
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
can safely be assumed to
D
ID = 55 A
150
17
0.1
0.05
0.02
(NORMALIZED)
0.01
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
0.2
0.1
0.01
SINGLE PULSE
P
(pk)
t, TIME (ms)
Figure 13. Thermal Response
di/dt
I
S
t
t
a
t
p
t
1
t
2
DUTY CYCLE, D = t1/t
rr
t
b
0.25 I
S
I
S
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
− TC = P
J(pk)
2
(pk)
1
R
(t)
q
JC
1.0 100.10.010.0010.00010.00001
TIME
Figure 14. Diode Reverse Recovery Waveform
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6
NTP60N06L, NTB60N06L
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
−B−
4
231
−T−
SEATING
PLANE
VARIABLE
CONFIGURATION
ZONE
G
M
S
D
3 PL
0.13 (0.005) T
R
L
M
C
E
V
W
A
K
W
J
H
M
M
B
N P
U
L
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
F 0.310 0.350 7.87 8.89
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
L 0.052 0.072 1.32 1.83
M 0.280 0.320 7.11 8.13
N 0.197 REF 5.00 REF
P 0.079 REF 2.00 REF
R 0.039 REF 0.99 REF
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
L
MILLIMETERSINCHES
M
F
VIEW W−W VIEW W−W VIEW W−W
123
F
F
SOLDERING FOOTPRINT*
8.38
0.33
10.66
0.42
17.02
0.67
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1.016
3.05
0.12
SCALE 3:1
0.04
ǒ
inches
5.08
0.20
mm
Ǔ
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7
NTP60N06L, NTB60N06L
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
SEATING
−T−
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTP60N06L/D
8
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