ON Semiconductor NTMD3P03R2 Technical data

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NTMD3P03R2
Power MOSFET
−3.05 Amps, −30 Volts
Dual P−Channel SO−8
High Efficiency Components in a Dual SO−8 Package
High Density Power MOSFET with Low R
Miniature SO−8 Surface Mount Package − Saves Board Space
Diode Exhibits High Speed with Soft Recovery
I
Specified at Elevated Temperature
DSS
Avalanche Energy Specified
Mounting Information for the SO−8 Package is Provided
Applications
DC−DC Converters
Low Voltage Motor Control
Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MOSFET MAXIMUM RATINGS (T
Rating Symbol Value Unit
Drain−to−Source Voltage V Gate−to−Source Voltage − Continuous V Thermal Resistance −
Junction−to−Ambient (Note 1) Total Power Dissipation @ T Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4)
Thermal Resistance −
Junction−to−Ambient (Note 2) Total Power Dissipation @ T Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4)
Thermal Resistance −
Junction−to−Ambient (Note 3) Total Power Dissipation @ T Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4)
Operating and Storage
Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
= −30 Vdc, VGS = −4.5 Vdc, Peak
(V
DD
I
= −7.5 Apk, L = 5 mH, RG = 25 Ω)
L
Maximum Lead Temperature for Soldering
Purposes, 1/8 from case for 10 seconds
1. Minimum FR−4 or G−10 PCB, t = Steady State.
2. Mounted onto a 2 square FR−4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state.
3. Mounted onto a 2 square FR−4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds.
4. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
= 25°C
J
= 25°C unless otherwise noted)
J
= 25°C
A
= 25°C
A
= 25°C
A
DSS
R
P
I I
I
DM
R
P
I I
I
DM
R
P
I I
I
DM
TJ, T
E
T
DS(on)
GS
θ
JA
D D D
θ
JA
D D D
θ
JA
D D D
stg
AS
L
−30 V ±20 V
171
0.73
−2.34
−1.87
−8.0
100
1.25
−3.05
−2.44
−12
62.5
2.0
−3.86
−3.1
−15
−55 to +150
140 mJ
260 °C
°C/W
°C/W
°C/W
W
W
W
°C
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V
DSS
−30 V 85 m @ −10 V −3.05 A
R
TYP ID MAX
DS(ON)
P−Channel
D
G
S
MARKING DIAGRAM
A A A
A A A
A A A
8
1
SO−8 CASE 751 STYLE 11
ED3P03 = Device Code L = Assembly Location Y = Year WW = Work Week
PIN ASSIGNMENT
1 2
3 4
Top View
8 7
6 5
Source−1
Gate−1
Source−2
Gate−2
ED3P03 LYWW
Drain−1 Drain−1 Drain−2 Drain−2
ORDERING INFORMATION
Device Package Shipping
NTMD3P03R2 SO−8 2500/Tape & Reel †For information on tape and reel specifications,
including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. 1
1 Publication Order Number:
NTMD3P03R2/D
NTMD3P03R2
)
f
MHz)
R
G
6.0 )
R
G
6.0 )
(V
24 Vdc
GS
)
dIS/dt
100 A/µs)
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted) (Note 5)
J
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
= 0 Vdc, ID = −250 µAdc)
(V
GS
Temperature Coefficient (Positive) Zero Gate Voltage Drain Current
(V
= −24 Vdc, VGS = 0 Vdc, TJ = 25°C)
DS
= −24 Vdc, VGS = 0 Vdc, TJ = 125°C)
(V
DS
(V
= −30 Vdc, VGS = 0 Vdc, TJ = 25°C)
DS
Gate−Body Leakage Current
(V
= −20 Vdc, VDS = 0 Vdc)
GS
Gate−Body Leakage Current
(V
= +20 Vdc, VDS = 0 Vdc)
GS
ON CHARACTERISTICS
Gate Threshold Voltage
(V
= VGS, ID = −250 µAdc)
DS
Temperature Coefficient (Negative) Static Drain−to−Source On−State Resistance
(V
= −10 Vdc, ID = −3.05 Adc)
GS
= −4.5 Vdc, ID = −1.5 Adc)
(V
GS
Forward Transconductance (VDS = −15 Vdc, ID = −3.05 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance
(VDS = −24 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
= 1.0
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 6 and 7)
Turn−On Delay Time Rise Time Turn−Off Delay Time
(VDD = −24 Vdc, ID = −3.05 Adc,
VGS = −10 Vdc,
= 6.0 Ω)
R
G
Fall Time Turn−On Delay Time t Rise Time Turn−Off Delay Time
(VDD = −24 Vdc, ID = −1.5 Adc,
VGS = −4.5 Vdc,
= 6.0 Ω)
R
G
Fall Time Total Gate Charge Gate−Source Charge Gate−Drain Charge
=−
= −
DS
= −10 Vdc,
V
GS
ID = −3.05 Adc)
,
BODY−DRAIN DIODE RATINGS (Note 6)
Diode Forward On−Voltage
(IS = −3.05 Adc, VGS = 0 V)
(I
= −3.05 Adc, VGS = 0 V, TJ = 125°C)
S
Reverse Recovery Time
(IS = −3.05 Adc, VGS = 0 Vdc,
dI
/dt = 100 A/µs
=
Reverse Recovery Stored Charge Q
5. Handling precautions to protect against electrostatic discharge is mandatory.
6. Indicates Pulse Test: Pulse Width =300 µs max, Duty Cycle = 2%.
7. Switching characteristics are independent of operating junction temperature.
V
(BR)DSS
I
DSS
I
GSS
I
GSS
V
GS(th)
R
DS(on)
C C C
t
d(on)
t
d(off)
d(on)
t
d(off)
Q
Q
Q
V
t t t
FS
iss oss rss
t
r
t
f
t
r
t
f tot gs gd
SD
rr
a
b RR
−30
−30
−1.0
−20
−2.0
mV/°C
−100
100
−1.0
−1.7
3.6
0.063
0.090
−2.5
0.085
0.125
5.0 Mhos
520 750 pF
170 325
70 135
12 22
16 30
45 80
45 80
16
42
32
35
16 25
2.0
4.5
−0.96
−0.78
−1.25
34
18
16
0.03 µC
Vdc
µAdc
nAdc
nAdc
Vdc
ns
ns
nC
Vdc
ns
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2
NTMD3P03R2
TYPICAL ELECTRICAL CHARACTERISTICS
6
5
VGS = −10 V
VGS = −8 V
VGS = −6 V
4
TJ = 25°C
3
2
, DRAIN CURRENT (AMPS)
D
1
−I 0
0
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−V
DS
VGS = −5 V
0.50.25
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.7
0.6
0.5
0.4
VGS = −2.6 V
0.75
VGS = −4.4 V
VGS = −4 V
VGS = −4.6 V
VGS = −4.8 V
VGS = −3.6 V
VGS = −2.8 V
VGS = −3.2 V
VGS = −3 V
1 1.25 1.5 1.75
ID = −3.05 A T
= 25°C
J
6
VDS > = −10 V
5
4
3
2
, DRAIN CURRENT (AMPS)
D
1
−I 0
2
14325
−V
0.7
0.6
0.5
0.4
TJ = 100°C
TJ = 25°C
TJ = −55°C
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
ID = −1.5 A T
= 25°C
J
0.3
0.2
0.1
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0
DS(on)
3
R
48
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
0.25 TJ = 25°C
0.2
0.15
0.1
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0.05
13254
DS(on)
R
−ID, DRAIN CURRENT (AMPS)
Figure 5. On−Resistance vs. Drain Current and
Voltage
VGS = −4.5 V
VGS = −10 V
Gate Voltage
0.3
0.2
0.1
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0
765
DS(on)
R
2
37
654
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 4. On−Resistance vs. Gate−to−Source
Voltage
1.6 ID = −3.05 A V
= −10 V
1.4
GS
1.2
1
(NORMALIZED)
0.8
, DRAIN−TO−SOURCE RESISTANCE
6
−50 50 75250 150−25
100 125
0.6
DS(on)
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. On Resistance Variation with
Temperature
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3
NTMD3P03R2
10000
VGS = 0 V
TJ = 150°C
1200
1000
VDS = 0 V VGS = 0 V
C
iss
1000
800
C
TJ = 125°C
, LEAKAGE (nA)
100
DSS
I
10
6182214 2610 30
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−V
DS
C
600
400
C, CAPACITANCE (pF)
rss
200
TJ = 25°C
0
10 15 20105530025
−V
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
iss
C
oss
C
rss
−V
DS
VOLTAGE (VOLTS)
Figure 7. Drain−to−Source Leakage Current
Figure 8. Capacitance Variation
vs. Voltage
12
Q
10
V
DS
T
8
V
GS
6
Q
1
4
2
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
GS
0 8 16 1 100
−V
246 101214
Q
2
ID = −3.05 A T
= 25°C
J
Qg, TOTAL GATE CHARGE (nC)
30
25
20
15
10
5
0
1000
100
t, TIME (ns)
10
1
VDS = −24 V I
= −3.05 A
D
V
= −10 V
GS
t
d(off)
t
f
t
r
t
d(on)
10
RG, GATE RESISTANCE (Ω)
Figure 9. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
VDS = −24 V I
= −1.5 A
D
= −4.5 V
V
GS
100
t, TIME (ns)
10
1 10010 0.2 1 1.20.80.60.4
t
r
t
f
t
d(off)
t
d(on)
, SOURCE CURRENT (AMPS)
S
I
RG, GATE RESISTANCE (Ω)
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
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4
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
3
VGS = 0 V T
= 25°C
J
2.5
2
1.5
1
0.5
0
−VSD, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Diode Forward Voltage vs. Current
100
VGS = 12 V SINGLE PULSE
= 25°C
T
C
10
1.0
0.1
, DRAIN CURRENT (AMPS)
D
−I
dc
R
LIMIT
DS(on)
THERMAL LIMIT PACKAGE LIMIT
0.01 1 10010
1.0
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
1.0 D = 0.5
10 ms
1.0 ms
NTMD3P03R2
di/dt
I
S
t
rr
t
t
a
b
TIME
I
S
0.25 I
S
t
p
Figure 14. Diode Reverse Recovery Waveform
0.2
0.1
0.1
0.05
0.02
, EFFECTIVE TRANSIENT
THERMAL RESPONSE
thja(t)
R
0.01 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03
Single Pulse
0.01
Chip Junction
0.0014 F 0.0073 F 0.022 F 0.105 F 0.484 F
Normalized to R
2.32 18.5 50.9 37.1 56.8
at Steady State (1 pad)
θ
JA
24.4
3.68 F Ambient
t, TIME (s)
Figure 15. FET Thermal Response
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5
−Y−
−Z−
NTMD3P03R2
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE AB
−X−
B
H
A
58
1
4
G
D
0.25 (0.010) Z
M
S
SXS
Y
0.25 (0.010)
C
SEATING PLANE
M
0.10 (0.004)
M
Y
K
N
X 45
M
J
SOLDERING FOOTPRINT*
1.52
0.060
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050
M 0 8 0 8

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
INCHES
7.0
0.275
0.6
0.024
4.0
0.155
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NTMD3P03R2/D
6
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