ON Semiconductor NTMD2C02R2 Technical data

查询NTMD2C02R2供应商

NTMD2C02R2

Preferred Device

Power MOSFET
2 Amps, 20 Volts

Complementary SO–8, Dual

These miniature surface mount MOSFET s feature ultra low R

DS(on)

and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives.

• Ultra Low R

Provides Higher Efficiency and Extends

DS(on)

Battery Life

• Logic Level Gate Drive – Can Be Driven by Logic ICs

• Miniature SO–8 Surface Mount Package – Saves Board Space

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, With Soft Recovery

• I

Specified at Elevated Temperature

DSS

• Mounting Information for SO–8 Package Provided

MAXIMUM RATINGS (T

Rating

Drain–to–Source Voltage

N–Channel

P–Channel
Gate–to–Source Voltage V
Drain Current – Continuous N–Channel

– Pulsed N–Channel

Operating and Storage Temperature Range TJ and

Total Power Dissipation @ TA= 25°C

(Note 2)
Thermal Resistance – Junction to Ambient

(Note 2)
Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds.

1. Negative signs for P–Channel device omitted for clarity.

2. Mounted on 2 ″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with
one die operating, 10 sec. max.

= 25°C unless otherwise noted) (Note 1)

J

Symbol Value Unit

V

P–Channel

P–Channel

R

I

T

P

DSS

GS

I

D

DM

stg

D

θ

JA

T

L

20
20

±12 Vdc

5.2

3.4
48
17

–55 to

150

2.0 Watts

62.5 °C/W

260 °C

Vdc

A

°C

http://onsemi.com

2 AMPERES

20 VOLTS

R

DS(on)

R

DS(on)

G

D2C02 = Specific Device Code
L = Location Code
Y = Year
WW = Work Week

Device Package Shipping

= 43 m (N–Channel)

= 120 m (P–Channel)

N–Channel

D

G

S

8

1

SO–8, Dual

CASE 751
STYLE 14

PIN ASSIGNMENT

N–Source

N–Gate

P–Source

P–Gate

ORDERING INFORMATION

1
2
3
4

Top View

8
7
6
5

P–Channel

D

MARKING
DIAGRAM

D2C02
LYWW

N–Drain
N–Drain

P–Drain
P–Drain

S

 Semiconductor Components Industries, LLC, 2002

September, 2002 – Rev. 0

NTMD2C02R2 SO–8 2500/Tape & Reel

Preferred devices are recommended choices for future use
and best overall value.

1 Publication Order Number:

NTMD2C02R2/D

NTMD2C02R2

)

(V

DD

Vdc, I

D

Adc

V

GS

Vdc

(V

DS

Vdc, I

D

Adc

V

GS

Vdc

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted) (Note 3)

A

Characteristic Symbol Polarity Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

= 0 Vdc, ID = 250 µAdc)

(V

GS

Zero Gate Voltage Drain Current

(V

= 0 Vdc, VDS = 20 Vdc)

GS

= 0 Vdc, VDS = 12 Vdc)

(V

GS

Gate–Body Leakage Current

= ±12 Vdc, VDS = 0)

(V

GS

V

(BR)DSS

I

DSS

I

GSS

ON CHARACTERISTICS (Note 4)

Gate Threshold Voltage

= VGS, ID = 250 µAdc)

(V

DS

Drain–to–Source On–Resistance

(V

= 4.5 Vdc, ID = 4.0 Adc)

GS

= 4.5 Vdc, ID = 2.4 Adc)

(V

GS

Drain–to–Source On–Resistance

(V

= 2.7 Vdc, ID = 2.0 Adc)

GS

= 2.7 Vdc, ID = 1.2 Adc)

(V

GS

Forward Transconductance

(V

= 2.5 Vdc, ID = 2.0 Adc)

DS

= 2.5 Vdc, ID = 1.0 Adc)

(V

DS

V

GS(th)

R

DS(on)

R

DS(on)

g

FS

DYNAMIC CHARACTERISTICS

Input Capacitance

Output Capacitance

(VDS = 10 Vdc, VGS = 0 Vdc,

C

iss

C

oss

f = 1.0 MHz)

Transfer Capacitance

C

rss

SWITCHING CHARACTERISTICS (Note 5)

Turn–On Delay Time

Rise Time

Turn–Off Delay Time

Fall Time

Turn–On Delay Time

Rise Time

Turn–Off Delay Time

Fall Time

(VDD = 16 Vdc, ID = 4.0 Adc,

16

V

GS

R

= 4.5 Vdc,

= 6.0 Ω)

G

4.0

(VDD = 10 Vdc, ID = 1.2 Adc,

= 2.7 Vdc,

= 2.7

V

R

= 6.0 Ω)

G

(VDS = 16 Vdc, ID = 6.0 Adc,

16

= 4.5 Vdc,

V

GS

R

= 6.0 Ω)

G

(V

= 10 Vdc, ID = 2.4 Adc,

DS

V

= 4.5 Vdc,

= 4.5

= 6.0 Ω)

R

G

,

6.0

,

t

d(on)

,

t

r

t

d(off)

t

f

t

d(on)

,

t

r

t

d(off)

t

f

3. Negative signs for P–Channel device omitted for clarity.

4. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.

5. Switching characteristics are independent of operating junction temperature.

(N)
(P)

(N)
(P)

20
20

–
–

–
–

–
–

– – – 100

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

0.6

0.6

–

0.07

–

0.1

3.0

3.0

–
–

–
–

–
–

–
–

–
–

–
–

–
–

–
–

–
–

–
–

–
–

0.9

0.9

0.028–0.043

0.033–0.048

0.13

6.0

4.75

785

1100

540
210

215

75

100

11
15

35
40

45
35

60
35

12
10

50
35

45
33

80
29

–
–

1.0

1.0

1.2

1.2

0.1

–
–

750
450

325
180

175

18

–

65

–

75

–

110

–

20
20

90
65

75
60

130

55

Vdc

µAdc

nAdc

Vdc

Ohm

Ohm

mhos

pF

ns

http://onsemi.com

2

NTMD2C02R2

)

V

GS

Vdc)

(

(I

F

I

S

ELECTRICAL CHARACTERISTICS – continued (T

= 25°C unless otherwise noted) (Note 6)

A

Characteristic Symbol Polarity Min Typ Max Unit

SWITCHING CHARACTERISTICS – continued (Note 8)

Total Gate Charge Q

Gate–Source Charge

Gate–Drain Charge

(VDS = 10 Vdc, ID = 4.0 Adc,

V

= 4.5 Vdc)

GS

(V

= 6.0 Vdc, ID = 2.0 Adc,

DS

V

= 4.5 Vdc

= 4.5

T

Q

1

Q

2

Q

3

SOURCE–DRAIN DIODE CHARACTERISTICS (TC = 25°C)

Forward Voltage (Note 7)

Reverse Recovery Time

Reverse Recovery Stored

(IS = 4.0 Adc, VGS = 0 Vdc)
(I

= 2.4 Adc, VGS = 0 Vdc)

S

I

= I

,

=

dI

/dt = 100 A/µs)

S

,

V

SD

t

rr

t

a

t

b

Q

RR

Charge

6. Negative signs for P–Channel device omitted for clarity.

7. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.

8. Switching characteristics are independent of operating junction temperature.

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

–
–

–
–

–
–

–
–

–
–

–
–

–
–

–
–

–
–

12
10

1.5

1.5

4.0

5.0

3.0

3.0

0.83

0.88
30

37
15

16
15

21

0.02

0.025

20
18

1.1

1.0

nC

–
–

–
–

–
–

Vdc

–

ns

–
–

–
–

–
–

µC

–

http://onsemi.com

3

12

10

8

6

4

, DRAIN CURRENT (AMPS)

D

2

I

10 V

NTMD2C02R2

TYPICAL ELECTRICAL CHARACTERISTICS

N–Channel P–Channel

2.5 V

4.5 V

3.2 V

2.0 V

TJ = 25°C

1.8 V

VGS = 1.5 V

4

3

2

1

DRAIN CURRENT (AMPS)

D,

–I

VGS = –2.1 V

VGS = –10 V

= –4.5 V

V

GS

V

= –2.5 V

GS

TJ = 25°C

VGS = –1.9 V

VGS = –1.7 V

VGS = –1.5 V

0

12

10

8

6

4

, DRAIN CURRENT (AMPS)

2

D

I

0

V

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

DS

Figure 1. On–Region Characteristics

VDS ≥ 10 V

100°C

TJ = –55°C

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

25°C

Figure 2. Transfer Characteristics

1.751.51.2510.750.50.250

0

0

–V

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

DS

6

84210

Figure 1. On–Region Characteristics

5

VDS ≥ –10 V

4

3

2

TJ = 25°C

DRAIN CURRENT (AMPS)

1

D,

TJ = 100°C

–I

2.521.510.5

0

1

, GATE–TO–SOURCE VOLTAGE (VOLTS)

–V

GS

TJ = 55°C

1.5 2

2.5

3

Figure 2. Transfer Characteristics

http://onsemi.com

4

0

0.07

0.06

0.05

0.04

0.03

NTMD2C02R2

TYPICAL ELECTRICAL CHARACTERISTICS

N–Channel P–Channel

0.2

ID = 6.0 A
T

= 25°C

J

0.15

TJ = 25°C

0.1

0.02

0.01

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

0

DS(on)

R

0.05

0.04

0.03

0.02

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

0.01

DS(on)

R

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 4. On–Resistance versus Drain Current

Figure 3. On–Resistance versus

Gate–To–Source Voltage

TJ = 25°C

VGS = 2.5 V

4.5 V

7531

ID, DRAIN CURRENT (AMPS)

and Gate Voltage

0.05

, DRAIN–TO–SOURCE RESISTANCE ()

DS(on)

R

0.12

0.1

0.08

0.06

, DRAIN–TO–SOURCE RESISTANCE ()

0.04

DS(on)

R

0

2

TJ = 25°C

1

1086420

11913

Figure 4. On–Resistance versus Drain Current

46

–V

GATE–TO–SOURCE VOLTAGE (VOLTS)

GS,

Figure 3. On–Resistance versus

Gate–To–Source Voltage

VGS = –2.7 V

VGS = –4.5 V

1.5 2 2.5 3.5
–ID, DRAIN CURRENT (AMPS)

and Gate Voltage

8

4.543

1.6

1.4

1.2

1

(NORMALIZED)

0.8

, DRAIN–TO–SOURCE RESISTANCE

0.6

DS(on)

R

ID = 6.0 A
V

= 4.5 V

GS

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with

Temperature

http://onsemi.com

1.6

1.4

1.2

1

, DRAIN–TO–SOURCE

0.8

DS(on)

R

RESISTANCE (NORMALIZED)

1501251007550250–25–50

0.6
–50

5

ID = –2.4 A

V

= –4.5 V

GS

–25 0 25 75

T

JUNCTION TEMPERATURE (°C)

J,

Figure 5. On–Resistance Variation with

Temperature

15

12510050

NTMD2C02R2

TYPICAL ELECTRICAL CHARACTERISTICS

N–Channel P–Channel

1000

, LEAKAGE (nA)

I

100

10

DSS

0.1

0.01

VGS = 0 V

TJ = 125°C

100°C

1

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

25°C

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GG

GSP

– V

)

GSP

)]

1000

VGS = 0 V

100

10

LEAKAGE (nA)

1

DSS,

–I

0.1

20161284

0.01
–V

DS,

Figure 6. Drain–To–Source Leakage

The capacitance (C

TJ = 125°C

TJ = 100°C

TJ = 25°C

4 8 12 16

DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Current versus Voltage

) is read from the capacitance curve at

iss

200

a voltage corresponding to the off–state condition when
calculating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

http://onsemi.com

6

2500

,

2000

VDS = 0 V VGS = 0 V

C

iss

NTMD2C02R2

N–Channel P–Channel

1500

TJ = 25°C

1200

C

iss

VDS = 0 V VGS = 0 V

TJ = 25°C

1500

C

rss

1000

C, CAPACITANCE (pF)

500

C

rss

0

10 0 5 105

V

V

DS

GS

GATE–TO–SOURCE OR DRAIN–TO–SOURCE

VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

, GATE–TO–SOURCE VOLTAGE (VOLTS)

GS

V

5

4

V

DS

3

Q1

2

1

0

0

QT

V

GS

ID = 6 A
V

Q2

48 16

DS

V

GS

T

= 25°C

J

12

= 16 V
= 4.5 V

Qg, TOTAL GATE CHARGE (nC)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

C

iss

C

oss

15 20

20

16

12

8

4

0

900

C

rss

600

C, CAPACITANCE (pF)

300

0

5051015

–V

–V

GATE–TO–SOURCE OR DRAIN–TO–SOURCE

DS

GS

VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

5

QT

4

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

DS

V

3

2

1

GATE–TO–SOURCE VOLTAGE (VOLTS)

0

GS,

–V

Q1

Q2

V

DS

246 10 14

Q

, TOTAL GATE CHARGE (nC)

g

V

GS

ID = –2.4 A

80

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

T

J

C
C

= 25°C

12

C

iss

oss

rss

2010

20
18
16
14
12
10
8
6
4
2

0

DRAIN–TO–SOURCE VOLTAGE (VOLTS)

DS

–V

1000

VDS = 16 V
I

= 4.0 A

D

= 4.5 V

V

GS

100

t

t

d(off)

t

d(on)

f

t

r

t, TIME (ns)

10

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

1000

100

t, TIME (ns)

10

1.0

http://onsemi.com

7

VDD = –10 V

= –1.2 A

I

D

VGS = –2.7 V

t

r

t

d (off)

t

d (on)

R

GATE RESISTANCE (OHMS)

G,

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

t

f

10010

NTMD2C02R2

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
to the storage of minority carrier charge, Q

, as shown in

RR

, due

rr

the typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t

and low QRR specifications to

rr

minimize these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by

N–Channel P–Channel

5

VGS = 0 V
T

= 25°C

4

J

high di/dts. The diode’s negative di/dt during t

is directly

a

controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t

serves as a good indicator of recovery

b/ta

abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t

), have less stored charge and a softer

rr

reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.

2

VGS = 0 V

T

= 25°C

1.6

J

3

2

1

, SOURCE CURRENT (AMPS)

S

I

0

0 0.2 0.4 0.6

V

, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

SD

0.8 1.0

1.2

1.2

0.8

SOURCE CURRENT (AMPS)

0.4

S,

–I

0

SOURCE–TO–DRAIN VOLTAGE (VOLTS)

–V

SD,

Figure 10. Diode Forward Voltage versus Current Figure 10. Diode Forward Voltage versus Current

0.90.80.70.60.50.4

1

http://onsemi.com

8

NTMD2C02R2

di/dt = 300 A/µs

, SOURCE CURRENT

S

I

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T

) of 25°C.

C

Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”

Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(I

) nor rated voltage (V

DM

) is exceeded, and that the

DSS

transition time (tr, tf) does not exceed 10 µs. In addition the

Standard Cell Density

t

rr

High Cell Density

t

rr

t

b

t

a

t, TIME

total power averaged over a complete switching cycle must
not exceed (T

J(MAX)

– TC)/(R

).

JC

θ

A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non–linearly with an increase of peak current in avalanche
and peak junction temperature.

N–Channel P–Channel

100

VGS = 20 V

10

, DRAIN CURRENT (AMPS)

0.1

D

I

0.01

SINGLE PULSE
T

= 25°C

C

10 ms

1

Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.

0.1

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

V

DS

dc

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1

100 µs

1 ms

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

10

10 µs

100

100

10

, DRAIN CURRENT (AMPS)

0.1

D

I

0.01

VGS = 8 V
SINGLE PULSE

T

= 25°C

C

1

0.1

V

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

DS

Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.

1 ms

10 ms

dc

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1

10

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

100

http://onsemi.com

9

NTMD2C02R2

TYPICAL ELECTRICAL CHARACTERISTICS

10

1

D = 0.5

0.2

0.1

THERMAL RESISTANCE

0.01

Rthja(t), EFFECTIVE TRANSIENT

0.1

0.05

0.02

0.01

Normalized to θja at 10s.

0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω

Chip

SINGLE PULSE

0.001

1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

t

p

0.25 I

S

I

S

TIME

107.55 F1.7891 F0.3074 F0.0854 F0.0154 F

Ambient

1.0E+02 1.0E+03

Figure 14. Diode Reverse Recovery Waveform

http://onsemi.com

10

NTMD2C02R2

INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a c ritical p ortion o f t he total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection

0.275

7.0

0.024

0.6

SO–8 POWER DISSIPATION

The power dissipation of the SO–8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by T
temperature of the die, R

, the maximum rated junction

J(max)

, the thermal resistance from

JA

θ

the device junction to ambient; and the operating
temperature, T

. Using the values provided on the data

A

sheet for the SO–8 package, PD can be calculated as
follows:

PD =

J(max)

A

R

θ

JA

– T

T

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values

interface between the board and the package. With the
correct pad geometry, the packages will self–align when
subjected to a solder reflow process.

0.060

1.52

0.155

4.0

0.050

1.270

inches

mm

into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 2.0 Watts.

150°C – 25°C

PD =

62.5°C/W

= 2.0 Watts

The 62.5°C/W for the SO–8 package assumes the

recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Clad. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.

http://onsemi.com

• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.

• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied
during cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

11

NTMD2C02R2

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 15 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows

200°C

150°C

100°C

STEP 1

PREHEAT

ZONE 1
“RAMP”

DESIRED CURVE FOR HIGH

STEP 2

VENT

“SOAK”

MASS ASSEMBLIES

150°C

100°C

HEATING

ZONES 2 & 5

STEP 3

“RAMP”

temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177–189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

160°C

140°C

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT
SOLDER

JOINT

5°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL) T

Figure 15. Typical Solder Heating Profile

MAX

http://onsemi.com

12

–Y–

–Z–

NTMD2C02R2

PACKAGE DIMENSIONS

SO–8

CASE 751–07

ISSUE AA

NOTES:

–X–

A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

N

X 45



M

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDAARD IS 751-07

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020

G 1.27 BSC 0.050 BSC

H 0.10 0.25 0.004 0.010

J

J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050

M 0 8 0 8



N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

STYLE 14:

PIN 1. NSOURCE

2. NGATE

3. PSOURCE

4. PGATE

5. PDRAIN

6. PDRAIN

7. NDRAIN

8. NDRAIN

INCHES

http://onsemi.com

13

Notes

NTMD2C02R2

http://onsemi.com

14

Notes

NTMD2C02R2

http://onsemi.com

15

NTMD2C02R2

MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
Thermal Clad is a registered trademark of the Bergquist Company.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 Toll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

http://onsemi.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

NTMD2C02R2/D

16