ON Semiconductor NTGS5120P, NVGS5120P User Manual

NTGS5120P, NVGS5120P
MOSFET – Power, Single,
P-Channel, TSOP-6
-60 V, -2.9 A
60 V BVds, Low R
in TSOP6 Package
DS(on)
4.5 V Gate Rating
NV Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AECQ101 Qualified and PPAP Capable
This is a PbFree Device
Applications
High Side Load Switch
Power Switch for Printers, Communication Equipment
MAXIMUM RATINGS (T
Parameter
DraintoSource Voltage V
Gateto−Source Voltage V
Continuous Drain Current (Note 1)
Power Dissipation (Note 1)
Continuous Drain Current (Note 2)
Power Dissipation (Note 2)
Pulsed Drain Current
Operating Junction and Storage Temperature TJ,
Lead Temperature for Soldering Purposes (1/8” from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces)
2. Surfacemounted on FR4 board using the minimum recommended pad size.
= 25°C unless otherwise stated)
J
Symbol Value Unit
D
D
L
60 V
$20 V
2.5
1.1
1.8
0.6 W
20 A
55 to
150
260 °C
DSS
GS
T
I
P
I
P
I
DM
STG
T
D
D
Steady
State
t v 5 s TA = 25°C 2.9
Steady
State
t v 5 s 1.4
Steady
State
tp = 10 ms
TA = 25°C
TA = 85°C 2.0
TA = 25°C
TA = 25°C
TA = 85°C 1.3
TA = 25°C
A
W
A
°C
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V
(BR)DSS
60 V
R
MAX ID MAX
DS(ON)
111 m W @ −10 V
142 mW @ 4.5 V
PChannel
1256
3
4
2.9 A
MARKING DIAGRAM
TSOP−6
CASE 318G
1
XX = Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location)
STYLE 1
XX MG
G
1
PIN ASSIGNMENT
DrainDrain
Source
56
4
321
Drain
GateDrain
ORDERING INFORMATION
See detailed ordering and shipping information ion page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 1
1 Publication Order Number:
NTGS5120P/D
NTGS5120P, NVGS5120P
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
JunctiontoAmbient – Steady State (Note 3)
JunctiontoAmbient – t = 5 s (Note 3)
JunctiontoAmbient – Steady State (Note 4)
3. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces)
4. Surfacemounted on FR4 board using the minimum recommended pad size.
R
q
JA
R
q
JA
R
q
JA
102
77.6
200
°C/W
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
V
Zero Gate Voltage Drain Current I
GatetoSource Leakage Current I
(BR)DSS
DSS
GSS
VGS = 0 V, ID = 250 mA
VGS = 0 V,
V
= 48 V
DS
TJ = 25°C 1.0 mA
TJ = 125°C 5.0
VDS = 0 V, VGS = ±12 V $100 nA
60 V
VDS = 0 V, VGS = ±20 V $200 nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
DraintoSource On Resistance R
V
GS(TH)
DS(on)
VGS = VDS, ID = 250 mA
VGS = 10 V, ID = 2.9 A 72 111 mW
1.0 3.0 V
VGS = 4.5 V, ID = 2.5 A 88 142
Forward Transconductance g
FS
VDS = 5.0 V, ID = 6.0 A 10.1 S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
GatetoSource Charge Q
GatetoDrain Charge Q
C
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
VGS = 0 V, f = 1 MHz, VDS = 30 V
VGS = 10 V, VDS = 30 V;
ID = 2.9 A
942
72
48
18.1
1.2
2.7
3.6
pF
nC
SWITCHING CHARACTERISTICS (Note 6)
TurnOn Delay Time
t
Rise Time t
TurnOff Delay Time t
d(OFF)
Fall Time t
d(ON)
r
f
VGS = 10 V, VDS = 30 V,
= 1.0 A, RG = 6.0 W
I
D
8.7
4.9
38
12.8
ns
DRAINSOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Reverse Recovery Charge Q
V
SD
RR
a
RR
VGS = 0 V, I
= 0.9 A
S
TJ = 25°C 0.75 1.0 V
VGS = 0 V, dIS/dt = 100 A/ms,
I
= 0.9 A
S
18.3 ns
15.5 ns
15.1 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%
6. Switching characteristics are independent of operating junction temperatures
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2
NTGS5120P, NVGS5120P
TYPICAL CHARACTERISTICS
3.5
3.0
2.5
2.0
1.5
1.0
, DRAIN CURRENT (A)
D
I
0.5
0
3.0 V
10 V
3.2 V
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TOSOURCE VOLTAGE (V)
Figure 1. OnRegion Characteristics Figure 2. Transfer Characteristics
0.20
0.18
0.16
0.14
0.12
2.8 V
4.5 V
TJ = 25°C
2.6 V
2.4 V
VGS = 2.2 V
ID = 2.9 A
= 25°C
T
J
5.0
4.0
3.0
2.0
, DRAIN CURRENT (A)
D
I
1.0
3.02.52.01.51.00.50
0
0.10
0.09
0.08
0.07
VDS 10 V
TJ = 25°C
TJ = 55°C TJ = 25°C
TJ = 125°C
1.4 2.4 3.4
VGS = 4.5 V
VGS = 10 V
3.92.91.90.90.4
0.10
0.08
0.06
, DRAINTOSOURCE RESISTANCE (W)
0.04
DS(on)
R
VGS, GATE−TOSOURCE VOLTAGE (V) −ID, DRAIN CURRENT (A)
Figure 3. OnResistance vs. Gate Voltage Figure 4. On−Resistance vs. Drain Current and
1.8
1.6
1.4
1.2
1.0
, DRAINTOSOURCE RES-
ISTANCE (NORMALIZED)
0.8
DS(on)
R
0.6
ID = 2.9 A
= 4.5 V
V
GS
Figure 5. OnResistance Variation with
0.06
0.05
, DRAINTOSOURCE RESISTANCE (W)
6.0 7.0 8.0 9.0 6.0
105.04.03.02.0
0.04
DS(on)
R
Gate Voltage
10,000
VGS = 0 V
1000
, LEAKAGE (nA)
100
DSS
I
1251007550250−25−50
150
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAINTOSOURCE VOLTAGE (V)
10
TJ = 150°C
TJ = 125°C
5040302010
Figure 6. DraintoSource Leakage Current
Temperature
vs. Voltage
7.05.04.03.02.01.0
60
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3
NTGS5120P, NVGS5120P
TYPICAL CHARACTERISTICS
1300 1200 1100 1000
900 800 700 600 500 400
C
300
C, CAPACITANCE (pF)
200 100
C
0
1000
100
10
VGS = 0 V
= 25°C
T
C
iss
J
9.0
8.0
Qt
7.0
6.0
5.0
rss
oss
4.0
3.0
Q
2.0
, GATE−TO−SOURCE VOLTAGE (V)
1.0
GS
0
V
3020100
40
Q
gs
gd
VDS, DRAIN−TOSOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total
Charge
1.4
VDD = 30 V
= 1.0 A
I
D
V
= 10 V
GS
t
d(off)
t
f
1.2
1.0
0.8
VGS = 0 V
= 25°C
T
J
TJ = 25°C
= 2.9 A
I
D
Vds = 30 V
161410 12
188.06.02.0 4.00
t, TIME (ns)
10
1.0
Figure 9. Resistive Switching Time Variation
t
d(on)
RG, GATE RESISTANCE (W)
vs. Gate Resistance
100
10
1
0 V VGS 20 V SINGLE PULSE TC = 25°C
0.1
, DRAIN CURRENT (AMPS)
D
I
0.01
0.1 1 100 V
DS
Figure 11. Maximum Rated Forward Biased
0.6
t
r
0.4
, SOURCE CURRENT (A)
S
I
0.2
0
100101.0
V
SD
Figure 10. Diode Forward Voltage vs. Current
R
LIMIT
DS(on)
THERMAL LIMIT PACKAGE LIMIT
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Safe Operating Area
0.70.60.50.40.30.20.10
, SOURCETODRAIN VOLTAGE (V)
10 ms
100 ms
1 ms
10 ms
dc
0.90.8
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4
1000
, TRANSIENT THERMAL RESPONSE (°C/W)
thja(t)
R
100
10
0.1
0.01
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.00001 0.0001 0.0010.000001
NTGS5120P, NVGS5120P
TYPICAL CHARACTERISTICS
0.01 0.1 1 10 100 1000
t, PULSE TIME (s)
Figure 12. Thermal Response
Table 1. ORDERING INFORMATION
Marking
Part Number
NTGS5120PT1G P6 TSOP6
NVGS5120PT1G VP6 TSOP6
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
(XX)
Package Shipping
3000 / Tape & Reel
(PbFree)
3000 / Tape & Reel
(PbFree)
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
1
SCALE 2:1
D
456
E1
NOTE 5
0.05
A1
23
1
e
E
b
A
DETAIL Z
c
CASE 318G02
H
L
M
DETAIL Z
TSOP−6
ISSUE V
L2
GAUGE PLANE
SEATING
C
PLANE
DATE 12 JUN 2012
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
DIMAMIN NOM MAX
A1 0.01 0.06 0.10
b 0.25 0.38 0.50 c 0.10 0.18 0.26 D 2.90 3.00 3.10 E 2.50 2.75 3.00
E1
e 0.85 0.95 1.05 L 0.20 0.40 0.60
L2
M
MILLIMETERS
0.90 1.00 1.10
1.30 1.50 1.70
0.25 BSC
0° 10°
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
3.20
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
6X
0.95
0.95 PITCH
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)
4. D(IN)
5. VBUS
6. D(IN)+
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
GENERIC
MARKING DIAGRAM*
XXXAYWG
G
1
XXX = Specific Device Code A =Assembly Location Y = Year
XXX = Specific Device Code M = Date Code
G = Pb−Free Package W = Work Week G = Pb−Free Package
*This information is generic. Please refer to device data sheet
for actual part marking. PbFree indicator, “G” or microdot “ G”, may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
XXX MG
G
1
STANDARDIC
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© Semiconductor Components Industries, LLC, 2019
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