查询NTB75N03R供应商
NTB75N03R, NTP75N03R
Power MOSFET
75 Amps, 25 Volts
2
N−Channel D
PAK, TO−220
Features
• Planar HD3e Process for Fast Switching Performance
• Low R
• Low C
to Minimize Conduction Loss
DS(on)
to Minimize Driver Loss
iss
• Low Gate Charge
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V
Gate−to−Source Voltage − Continuous V
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ T
− Single Pulse (t
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T
Drain Current − Continuous @ T
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T
Drain Current − Continuous @ T
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
(V
= 30 Vdc, V
DD
L = 1 mH, R
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in
p
J
= 10 Vdc, IL = 12 Apk,
GS
= 25 )
G
= 25°C Unless otherwise specified)
J
= 25°C
C
= 10 s)
= 25°C
A
= 25°C
A
= 25°C
A
= 25°C
A
= 25°C
2
).
2
).
Symbol Value Unit
stg
25 V
±20 V
1.68
74.4
75
225
60
2.08
12.6
100
1.25
9.7
−55 to
150
71.7 mJ
260 °C
°C/W
°C/W
°C/W
R
R
R
P
I
P
P
E
DSS
GS
JC
D
I
D
DM
JA
D
I
D
JA
D
I
D
AS
T
L
W
W
W
°C
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75 AMPERES
25 VOLTS
R
DS(on)
dc
dc
A
A
A
A
1
2
Gate
3
4
Drain
P75N03R
YWW
1
Drain
ORDERING INFORMATION
Device Package Shipping
= 5.6 mΩ (Typ)
4
1
TO−220AB
CASE 221A
STYLE 5
MARKING DIAGRAMS
& PIN ASSIGNMENTS
3
Source
2
75N03 = Device Code
Y = Year
WW = Work Week
1
Gate
2
3
D2PAK
CASE 418AA
STYLE 2
4
Drain
75N03R
YWW
2
Drain
3
Source
4
†
Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 2
NTP75N03R TO−220AB 50 Units/Rail
NTB75N03R D2PAK 50 Units/Rail
NTB75N03RT4 D2PAK 800/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1 Publication Order Number:
NTB75N03R/D
NTB75N03R, NTP75N03R
)
f = 1 MHz)
(
(V
GS
V
d
V
DD
V
d
)
V
DS
V
d
) (Note 3)
g
Forward On−Voltage
V
SD
V
d
(
S dc,GS dc
)( )
(I
S
A
d
V
GS
V
d
ELECTRICAL CHARACTERISTICS (T
Characteristics
= 25°C Unless otherwise specified)
J
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(V
= 0 Vdc, I
GS
Temperature Coefficient (Positive)
= 250 Adc)
D
V
Zero Gate Voltage Drain Current
(V
= 20 Vdc, VGS = 0 Vdc)
DS
= 20 Vdc, VGS = 0 Vdc, TJ = 150°C)
(V
DS
Gate−Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
V
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
R
(VGS = 4.5 Vdc, ID = 20 Adc)
(V
= 10 Vdc, ID = 20 Adc)
GS
Forward Transconductance (Note 3)
(VDS = 10 Vdc, ID = 15 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 20 Vdc, VGS = 0 V,
f = 1 MHz
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time t
Rise Time
Turn−Off Delay Time
V
= 10 V
= 10
ID = 30 Adc, RG = 3)
, V
,
c
= 10 V
= 10
,
,
c
Fall Time t
Gate Charge
(VGS = 5 Vdc, ID = 30 Adc,
= 10
V
= 10 V) (Note 3
c
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Volta
e V
(IS = 20 Adc, VGS = 0 Vdc) (Note 3)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) − 0.73 −
Reverse Recovery Time
(I
= 35 A
= 35
dIS/dt = 100 A/s) (Note 3)
, V
= 0 V
= 0
,
,
c
,
c
Reverse Recovery Stored Charge Q
3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperatures.
(br)DSS
I
DSS
I
GSS
GS(th)
DS(on)
g
FS
C
iss
C
oss
C
rss
d(on)
t
r
t
d(off)
f
Q
T
Q
1
Q
2
D
t
rr
t
a
t
b
RR
25
−
−
−
28
20.5
−
−
1.0
10
−
−
mV/°C
− − ±100
1.0
−
−
−
1.5
4.0
8.1
5.6
2.0
13
8.0
−
mV/°C
Mhos
− 27 −
− 1333 −
− 600 −
− 218 −
− 6.9 −
− 1.3 −
− 18.4 −
− 5.5 −
− 13.2 −
− 3.3 −
− 6.2 −
− 0.86
1.2
− 15.6 −
− 13.8 −
− 1.78 −
− 0.004 − C
V
A
nA
V
m
V
dc
dc
dc
dc
pF
ns
nC
c
ns
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2
NTB75N03R, NTP75N03R
140
10 V
120
100
80
5 V
8 V
6 V
4.5 V
4 V
3.5 V
60
40
, DRAIN CURRENT (AMPS)
D
I
20
3 V
VGS = 2.5 V
0
010
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
42
6
8
140
VDS ≥ 10 V
120
100
80
60
TJ = 25°C
40
, DRAIN CURRENT (AMPS)
D
I
20
TJ = 125°C
0
10
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
GS
23
TJ = −55°C
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.022
0.018
0.014
0.010
0.006
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0.002
DS(on)
R
VGS = 10 V
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = −55°C
20 80
0
6040
100
120 140
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
0.022
0.018
0.014
0.010
0.006
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0.002
DS(on)
R
VGS = 4.5 V
TJ = 125°C
TJ = 25°C
TJ = −55°C
0
20 100
6040
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Temperature
45
TJ = 150°C
80
120
6
140
1.8
ID = 30 A
V
1.6
GS
= 10 V
1.4
1.2
1.0
(NORMALIZED)
0.8
, DRAIN−TO−SOURCE RESISTANCE
0.6
DS(on)
−50 50250−25 75 125100
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
100,000
10,000
, LEAKAGE (nA)
1000
DSS
I
100
150
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3
VGS = 0 V
TJ = 150°C
TJ = 125°C
01510 255
20
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus V oltage
NTB75N03R, NTP75N03R
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
2400
C
2000
1600
1200
C, CAPACITANCE (pF)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
iss
C
rss
800
400
0
10 0 10 15 20
55
Figure 7. Capacitance Variation
VGS = 0 VVDS = 0 V
V
V
GS
DS
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4
TJ = 25°C
C
C
iss
C
oss
rss
NTB75N03R, NTP75N03R
8
6
Q
T
4
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V
Q
1
2
0
0
Q
Q
2
48
, TOTAL GATE CHARGE (nC)
G
ID = 35 A
= 25°C
T
J
12
Figure 8. Gate−T o−Source and Drain−To−Source
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
70
VGS = 0 V
60
50
1000
V
GS
16
100
t
t, TIME (ns)
10
1
1 10 100
d(off)
t
d(on)
t
f
t
r
RG, GATE RESISTANCE (OHMS)
VDS = 10 V
I
= 35 A
D
V
GS
= 10 V
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
40
30
20
, SOURCE CURRENT (AMPS)
10
S
I
0
0
0.2 0.4 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
) nor rated voltage (V
DM
) is exceeded and the
DSS
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− TC)/(R
).
JC
θ
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
TJ = 150°C
TJ = 25°C
0.6 0.8
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
), the energy rating is specified at rated
DM
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum e ner gy a t
currents below rated continuous I
can safely be assumed to
D
equal the values indicated.
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5
1000
100
NTB75N03R, NTP75N03R
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
T
= 25°C
C
10 µs
100 µs
10
, DRAIN CURRENT (AMPS)
D
I
1
0.1 1 100
1
D = 0.5
0.2
0.1
0.05
0.01
RESISTANCE (NORMALIZED)
SINGLE PULSE
0.1
r(t), EFFECTIVE TRANSIENT THERMAL
0.001
1 ms
R
LIMIT
DS(on)
THERMAL LIMIT
10 ms
dc
PACKAGE LIMIT
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
t, TIME (s)
2
R
(t) = r(t) R
θ
JC
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
− TC = P
J(pk)
(pk)
1
R
(t)
θ
JC
1100.10.010.0001
Figure 12. Thermal Response
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6
NTB75N03R, NTP75N03R
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
−T−
SEATING
PLANE
VARIABLE
CONFIGURATION
ZONE
M
−B−
G
C
E
V
4
W
A
231
S
K
W
J
3 PL
D
M
0.13 (0.005) T
M
B
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.036 0.51 0.92
E 0.045 0.055 1.14 1.40
F 0.310 −−− 7.87 −−−
G 0.100 BSC 2.54 BSC
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
M 0.280 −−− 7.11 −−−
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
U
M
M
F
VIEW W−W VIEW W−W VIEW W−W
123
F
F
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7
NTB75N03R, NTP75N03R
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
SEATING
−T−
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NTB75N03R/D
8
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