Figure 1. On–Region CharacteristicsFigure 2. Transfer Characteristics
0.095
VGS = 10 V
0.085
0.075
0.065
0.055
0.045
0.035
0.025
, DRAIN–TO–SOURCE RESISTANCE (Ω)
0.015
032241684056
DS(on)
R
TJ = 100°C
TJ = 25°C
TJ = –55°C
48
ID, DRAIN CURRENT (AMPS)
0.095
0.085
0.075
0.065
0.055
0.045
0.035
0.025
, DRAIN–TO–SOURCE RESISTANCE (Ω)
0.015
DS(on)
R
VGS = 15 V
032241684056
TJ = 25°C
TJ = 100°C
TJ = –55°C
4.255.86.67.4
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
TJ = 100°C
TJ = 25°C
TJ = –55°C
48
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus
Gate–to–Source Voltage
2.2
ID = 13.5 A
VGS = 10 V
1.8
1.4
1
0.6
–5050250–2575100
, DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
DS(on)
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
10000
1000
100
, LEAKAGE (nA)
10
DSS
I
1
175150125
0405030201060
http://onsemi.com
3
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
TJ = 150°C
TJ = 125°C
TJ = 100°C
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–to–Source Leakage Current
versus V oltage
NTP27N06, NTB27N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
times may be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V
GSP
GSP
where
VGG = the gate drive voltage, which varies from zero to V
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(VGG – V
iss
In (VGG/V
iss
) can be made from a
G(AV)
. Therefore, rise and fall
SGP
)
)]
GSP
)
GSP
GG
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when
calculating t
on–state when calculating t
and is read at a voltage corresponding to the
d(on)
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1800
1600
C
1400
1200
1000
C, CAPACITANCE (pF)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
iss
C
rss
800
600
400
200
0
10010152025
55
VGS = 0 VVDS = 0 V
C
rss
V
GSVDS
Figure 7. Capacitance Variation
http://onsemi.com
4
TJ = 25°C
C
iss
C
oss
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