ON Semiconductor NTB125N02R, NTP125N02R Technical data

查询NTB125N02R供应商
NTB125N02R, NTP125N02R
Power MOSFET 125 A, 24 V N−Channel
TO−220, D
Features
Planar HD3e Process for Fast Switching Performance
Body Diode for Low t
Operation
Low C
Optimized Q
Low Gate Charge
to Minimize Driver Loss
iss
and R
gd
PAK
and Qrr and Optimized for Synchronous
rr
for Shoot−through Protection
DS(on)
http://onsemi.com
125 AMPERES, 24 VOLTS
R
DS(on)
= 3.7 m (Typ)
D
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V Gate−to−Source Voltage − Continuous V Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C Drain Current −
Continuous @ T Continuous @ T Continuous @ TA = 25°C, Limited by Wires Single Pulse (t
Thermal Resistance −
Junction−to−Ambient (Note 1) Total Power Dissipation @ T Drain Current − Continuous @ T
Thermal Resistance −
Junction−to−Ambient (Note 2) Total Power Dissipation @ T Drain Current − Continuous @ T
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche Energy − Starting T (V
= 50 Vdc, V
DD
L = 1 mH, R Maximum Lead Temperature for Soldering
Purposes, 1/8 from Case for 10 Seconds
1. When surface mounted to an FR4 board using 1 inch pad size, (Cu Area 1.127 in
2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in
= 25 )
G
C
C
= 10 s)
p
J
GS
= 25°C Unless otherwise specified)
J
= 25°C, Chip
= 25°C, Limited by Package
= 25°C
A
= 25°C
A
= 25°C
A
= 25°C
A
= 25°C
= 10 Vdc, IL = 15.5 Apk,
2
).
2
).
Symbol Value Unit
stg
24 V
±20 V
1.1
113.6 125
120.5
95
250
46
2.72
18.6
63
1.98
15.9
−55 to 150
120 mJ
260 °C
dc dc
°C/W
W
A A A A
°C/W
W
A
°C/W
W
A
°C
R
R
R
P
P
P
E
DSS
GS
JC D
I
D
I
D
I
D
I
D
JA D
I
D
JA D
I
D
AS
T
L
PIN ASSIGNMENT
PIN FUNCTION
1 Gate 2 Drain 3 Source 4 Drain
G
S
MARKING
DIAGRAMS
TO−220AB
4
CASE 221A
STYLE 5
1
2
3
2
D
4
2
1
3
125N2 = Specific Device Code Y = Year WW = Work Week
PAK
CASE 418AA
STYLE 2
125N2R
YWW
125N2
YWW
ORDERING INFORMATION
Device Package Shipping
2
NTB125N02R D NTB125N02RT4 D2PAK 800/Tape & Reel
NTP125N02R TO−220AB 50 Units/Rail †For information on tape and reel specifications,
including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
PAK
50 Units/Rail
Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 4
1 Publication Order Number:
NTB125N02R/D
NTB125N02R, NTP125N02R
(
DS dc,GS
,)
(
(V
GS
V
d
V
DD
V
d
)
V
DS
V
d
) (Note 3)
g
Forward On−Voltage
(I
S
A
d
V
GS
V
d
) (Note 3)
VSD−−0.82
1.2−V
d
(
S dc,GS dc
)
(I
S
A
d
V
GS
V
d
ELECTRICAL CHARACTERISTICS (T
Characteristics
= 25°C Unless otherwise specified)
J
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(V
= 0 Vdc, I
GS
Temperature Coefficient (Positive)
= 250 Adc)
D
Zero Gate Voltage Drain Current
(V
= 20 Vdc, VGS = 0 Vdc)
DS
= 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
(V
DS
Gate−Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc)
V
(BR)DSS
I
DSS
I
GSS
25
28 15
±100
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 110 Adc) (V
= 4.5 Vdc, ID = 55 Adc)
GS
(V
= 10 Vdc, ID = 20 Adc)
GS
= 4.5 Vdc, ID = 20 Adc)
(V
GS
Forward Transconductance (Note 3)
(VDS = 10 Vdc, ID = 15 Adc)
V
GS(th)
R
DS(on)
g
FS
1.0
1.5
5.0
3.7
4.9
3.7
4.7
44
DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance
(VDS = 20 Vdc, VGS = 0 V, f = 1 MHz)
C
iss
C
oss
C
rss
2710 3440
1105 1670
227 640
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time Rise Time Turn−Off Delay Time
V
= 10 V
= 10
ID = 40 Adc, RG = 3)
, V
,
c
= 10 V
= 10
t
d(on)
t
t
d(off)
r
,
,
c
11 22
39 80
27 40 Fall Time tf 21 40 Gate Charge
(VGS = 4.5 Vdc, ID = 40 Adc,
= 10
V
= 10 V) (Note 3
c
Q
T
Q
1
Q
2
23.6 28
5.1
11
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Volta
e (I
= 20 A
= 20
, V
= 0 V
,
= 0
c
(IS = 55 Adc, VGS = 0 Vdc)
) (Note 3) V
c
D
0.82 1.2 V
0.99
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) 0.65
Reverse Recovery Time
(I
= 30 A
= 30
dIS/dt = 100 A/s) (Note 3)
, V
= 0 V
= 0
,
,
c
,
c
Reverse Recovery Stored Charge Q
t t t
rr a b
RR
36.5
17.7
18.8
0.024 C
3. Pulse Test: Pulse Width  300 s, Duty Cycle 2%.
4. Switching characteristics are independent of operating junction temperatures.
1.5 10
2.0
4.6
6.2
V
dc
mV/°C
A
dc
nA
dc
V
dc
mV/°C
m
Mhos
pF
ns
nC
c
ns
http://onsemi.com
2
NTB125N02R, NTP125N02R
200
160
120
80
40
, DRAIN CURRENT (AMPS)
D
I
0
010
4.0 V
4.5 V
5.0 V
6.0 V
8.0 V
10 V
42
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
DS
6
3.5 V
3.0 V
VGS = 2.5 V
8
200
VDS 10 V
160
120
80
40
, DRAIN CURRENT (AMPS)
D
I
0
0 1.60.8
TJ = 25°C
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 125°C
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.01
0.008
0.006
0.004
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0.002
DS(on)
R
VGS = 10 V
TJ = 125°C
TJ = 25°C
TJ = −55°C
0
40 200
ID, DRAIN CURRENT (AMPS)
16012080
Figure 3. On−Resistance versus Drain Current
and Temperature
0.01 VGS = 4.5 V
0.008
0.006
0.004
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0.002
DS(on)
0 1601208040 200
R
ID, DRAIN CURRENT (AMPS)
TJ = 125°C
TJ = 25°C
TJ = −55°C
Figure 4. On−Resistance versus Drain Current
and Temperature
TJ = −55°C
2.4 3.2 4.0
1.8 ID = 55 A
V
1.6
1.4
1.2
1.0
(NORMALIZED)
0.8
, DRAIN−TO−SOURCE RESISTANCE
0.6
DS(on)
−50 50250−25 75 125100
R
= 4.5 V
GS
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
100,000
10,000
1000
, LEAKAGE (nA)
DSS
I
100
10
150
http://onsemi.com
3
VGS = 0 V
TJ = 150°C
TJ = 125°C
TJ = 100°C
016128.0 244.0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus V oltage
20
NTB125N02R, NTP125N02R
7000
6000
C
VDS = 0 V
iss
VGS = 0 V
5000
C
4000
3000
2000
C, CAPACITANCE (pF)
rss
C
iss
C
oss
1000
C
0
10
TJ = 25°C
5
10
V
V
GS
DS
rss
155020
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
1000
VDS = 10 V I
= 40 A
D
= 10 V
V
GS
10
8.0 V
GS
6.0
Q
4.0
Q
1
2.0
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
GS
V
0243216848
T
Q
2
, TOTAL GATE CHARGE (nC)
Q
g
ID = 40 A T
= 25°C
J
40
Drain−to−Source Voltage versus Total Charge
60
VGS = 0 V T
50
40
= 25°C
J
100
t, TIME (ns)
t
r
t
d(off)
t
f
t
10
d(on)
1 10 100 0 0.4 0.80.2 1.0
RG, GATE RESISTANCE (Ω)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
1000
VGS = 20 V
30
20
10
, SOURCE CURRENT (AMPS)
S
I
0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus
0.6
Current
SINGLE PULSE
= 25°C
T
C
100
100 s
1 ms
10
, DRAIN CURRENT (AMPS)
D
I
1.0
R
DS(on)
Thermal Limit Package Limit
Limit
10 ms
dc
0.1 10 1001.0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
4
NTB125N02R, NTP125N02R
1
Normalized to R
0.1
EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED)
r(t),
at Steady State
θ
JC
0.01
0.00001 10.10.010.0010.0001 10 t, TIME (s)
Figure 12. Thermal Response
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−09
ISSUE AA
SEATING
−T−
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED.
DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 V 0.045 −−− 1.15 −−− Z −−− 0.080 −−− 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
http://onsemi.com
5
−T−
SEATING PLANE
VARIABLE CONFIGURATION ZONE
−B−
G
NTB125N02R, NTP125N02R
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
C
E
V
4
W
A
231
S
K
W
J
3 PL
D
M
0.13 (0.005) T
M
B
U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65 B 0.380 0.405 9.65 10.29 C 0.160 0.190 4.06 4.83 D 0.020 0.036 0.51 0.92 E 0.045 0.055 1.14 1.40 F 0.310 −−− 7.87 −−− G 0.100 BSC 2.54 BSC J 0.018 0.025 0.46 0.64 K 0.090 0.110 2.29 2.79 M 0.280 −−− 7.11 −−− S 0.575 0.625 14.60 15.88 V 0.045 0.055 1.14 1.40
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
M
F
VIEW W−W VIEW W−W VIEW W−W
123
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
M
F
M
F
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
6
ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your local Sales Representative.
NTB125N02R/D
Loading...