ON Semiconductor NSTB1005DXV5T1, NSTB1005DXV5T5 Service Manual
NSTB1005DXV5T1,
NSTB1005DXV5T5
Preferred Devices
Dual Common
Base−Collector Bias
Resistor Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. The NSTB1005DXV5T1
contains two complementary BR T devices are housed i n the SOT−553
package which is ideal for low power surface mount applications
where board space is at a premium.
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch Tape and Reel
• Lead Free
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R1
Q1
45
CASE 463B
R2
Q2
R2
R1
5
1
SOT−553
MAXIMUM RATINGS (T
and Q2, − minus sign for Q1 (PNP) omitted)
Rating
Collector-Base Voltage V
Collector-Emitter Voltage V
Collector Current I
= 25°C unless otherwise noted, common for Q
A
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
T
= 25°C
A
Derate above 25°C
Thermal Resistance −
Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
T
= 25°C
A
Derate above 25°C
Thermal Resistance −
Junction-to-Ambient
Junction and Storage Temperature TJ, T
1. FR−4 @ Minimum Pad
Symbol Value Unit
CBO
CEO
C
Symbol Max Unit
P
D
R
JA
Symbol Max Unit
P
D
R
JA
stg
50 Vdc
50 Vdc
100 mAdc
357 (Note 1)
2.9 (Note 1)mWmW/°C
350 (Note 1) °C/W
500 (Note 1)
4.0 (Note 1)
250 (Note 1) °C/W
−55 to +150 °C
mW
mW/°C
1
MARKING DIAGRAM
5
UC D
1
UC = Specific Device Code
D = Date Code
ORDERING INFORMATION
Device Package Shipping
NSTB1005DXV5T1 SOT−553 4 mm pitch
4000/Tape & Reel
NSTB1005DXV5T5 SOT−553 2 mm pitch
8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
†
Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 0
1 Publication Order Number:
NSTB1005DXV5/D
NSTB1005DXV5T1, NSTB1005DXV5T5
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
A
Symbol Min Typ Max Unit
Q1 TRANSISTOR: PNP − OFF CHARACTERISTICS
Collector−Base Cutoff Current (V
= 50 V, IE = 0) I
CB
Collector−Emitter Cutoff Current (VCE = 50 V, IB = 0) I
Emitter−Base Cutoff Current I
Collector−Base Breakdown Voltage (IC = 10 A, IE = 0) V
Collector−Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
CBO
CEO
EBO
(BR)CBO
(BR)CEO
− − 100 nAdc
− − 500 nAdc
− − 0.1 mAdc
50 − − Vdc
50 − − Vdc
ON CHARACTERISTICS
DC Current Gain h
Collector−Emitter Saturation Voltage (IC = 10 mA, IE = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, VB = 3.5 V, RL = 1.0 k) V
Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k) V
FE
CE(sat)
OL
OH
80 140 −
− − 0.25 Vdc
− − 0.2 Vdc
4.9 − − Vdc
Input Resistor R1 32.9 47 61.1 k
Resistor Ratio R1/R
0.8 1.0 1.2
2
Q2 TRANSISTOR: NPN − OFF CHARACTERISTICS
Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I
Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) I
CBO
CEO
EBO
− − 100 nAdc
− − 500 nAdc
− − 0.1 mAdc
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (I
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
= 10 A, IE = 0) V
C
(BR)CBO
(BR)CEO
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, V
Output Voltage (off) (VCC = 5.0 V, V
= 2.5 V, RL = 1.0 k) V
B
= 0.5 V, RL = 1.0 k) V
B
CE(SAT)
FE
OL
OH
50 − − Vdc
50 − − Vdc
80 140 −
− − 0.25 Vdc
− − 0.2 Vdc
4.9 − − Vdc
Input Resistor R1 33 47 61 k
Resistor Ratio R1/R2 0.8 1.0 1.2
250
200
150
100
R
= 833°C/W
50
, POWER DISSIPATION (MILLIWATTS)
D
P
0
−50 0 50 100 150
JA
T
, AMBIENT TEMPERATURE (°C)
A
Figure 1. Derating Curve
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