ON Semiconductor NE570 Technical data

NE570

;

Compandor

The NE570 is a versatile low cost dual gain control circuit in which either channel may be used as a dynamic range compressor or expandor. Each channel has a full−wave rectifier to detect the average value of the signal, a linerarized temperature−compensated variable gain cell, and an operational amplifier.

The NE570 is well suited for use in cellular radio and radio communications systems, modems, telephone, and satellite broadcast/receive audio systems.

Features

• Complete Compressor and Expandor in One IC

• Temperature Compensated

• Greater than 110 dB Dynamic Range

• Operates Down to 6.0 V

• System Levels Adjustable with External Components

• Distortion may be Trimmed Out

• Pb−Free Packages are Available*

Applications

• Cellular Radio

• Telephone Trunk Comandor

• High Level Limiter

• Low Level Expandor − Noise Gate

• Dynamic Noise Reduction Systems

• Voltage−Controlled Amplifier

• Dynamic Filters

MAXIMUM RATINGS

Rating Symbol Value Unit

Maximum Operating Voltage V Operating Ambient Temperature Range T Operating Junction Temperature T Power Dissipation P Thermal Resistance, Junction−to−Ambient

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

DG CELL IN

RECT IN

THD TRIM

R2 20 kW

R1 10 kW

VARIABLE

GAIN

RECTIFIER

24 V

0 to +70 °C

150 °C 400 mW 105 °C/W

20 kW

30 kW

1.8 V

INVERTER IN

REF

−

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MARKING DIAGRAM

SOIC−16 WB

D SUFFIX

CASE 751G

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package

Plastic Small Outline Package

16 Leads; Body Width 7.5 mm

NE570D

AWLYYWWG

PIN CONNECTIONS

RECT_CAP_1

RECT_IN_1

DG_CELL_IN_1

GND

INV_IN_1

RES_R3_1

OUTPUT_1

THD_TRIM_1

1 2 3 4 5 6 7 8

(Top View)

RECT_CAP_2

16 15

RECT_IN_2

DG_CELL_IN_ V

INV_IN_2

RES_R3_2

OUTPUT_2

THD_TRIM_2

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

OUTPUT

RECT CAP

Figure 1. Block Diagram

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

May, 2006 − Rev. 4

1 Publication Order Number:

NE570/D

NE570

PIN FUNCTION DESCRIPTION

Pin Symbol Description

1 RECT CAP 1 External Capacitor Pinout for Rectifier 1 2 RECT IN 1 Rectifier 1 Input 3

DG CELL IN 1 4 GND Ground 5 INV. IN 1 Inverted Input 1 6 RES. R3 1 R3 Pinout 1 7 OUTPUT 1 Output 1 8 THD TRIM 1 Total Harmonic Distortion Trim 1 9 THD TRIM 2 Total Harmonic Distortion Trim 2

10 OUTPUT 2 Output 2 11 RES. R3 2 R3 Pinout 2 12 INV. IN 2 Inverted Input 2 13 V 14

DG CELL IN 2

15 RECT IN 2 Rectifier 2 Input 16 RECT CAP 2 External Capacitor Pinout for Rectifier 2

Variable Gain Cell 1 Input

Positive Power Supply Variable Gain Cell 2 Input

ELECTRICAL CHARACTERISTICS V

= +15 V, TA = 25 °C; unless otherwise stated.

Characteristic Test Conditions Symbol Min Typ Max Unit

Supply Voltage V Supply Current No Signal I Output Current Capability I

OUT

6.0 − 24 V

− 4.3 4.8 mA

±20 − − mA Output Slew Rate SR − ±0.5 − Gain Cell Distortion (Note 1)

Untrimmed − 0.3 1.0 %

Trimmed − 0.05 − % Resistor Tolerance − ±5 ±15 % Internal Reference Voltage 1.7 1.8 1.9 V Output DC Shift (Note 2) Untrimmed − ±90 ±150 mV Expandor Output Noise No signal, 15 Hz to 20 kHz

− 20 45

(Note 3) Unity Gain Level (Note 4) −1.0 0 +1.0 dBm Gain Change (Notes 1 and 5) TA = 0°C to +70°C − ±0.1 ±0.2 dB Reference Drift (Note 5) TA = 0°C to +70°C − ±5.0 ±10 mV Resistor Drift (Note 5) TA = 0°C to +70°C − +8.0, −5.0 − % Tracking Error (measured relative to value at unity gain)

equals [VO − VO (unity gain)] dB − V2 dBm

Rectifier Input VCC = +6.0 V

V2 = +6.0 dBm, V1 = 0 dB

V2 = −30 dBm, V1 = 0 dB

−

±0.2 +0.2−−0.5, +1.0dBdB

Channel Separation − 60 − dB

1. Measured at 0 dBm, 1.0 kHz.

2. Expandor AC input change from no signal to 0 dBm.

3. Input to V1 and V2 grounded.

4. 0 dB = 775 mV

5. Relative to value at TA = 25°C.

RMS

V/ms

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NE570

CIRCUIT DESCRIPTION

The NE570 compandor building blocks, as shown in the block diagram, are a full−wave rectifier, a variable gain cell, an operational amplifier and a bias system. The arrangement of these blocks in the IC result in a circuit which can perform well with few external components, yet can be adapted to many diverse applications.

The full−wave rectifier rectifies the input current which flows from the rectifier input, to an internal summing node which is biased at V an external filter capacitor tied to the C

. The rectified current is averaged on

REF

terminal, and

RECT

the average value of the input current controls the gain of the variable gain cell. The gain will thus be proportional to the average value of the input signal for capacitively−coupled voltage inputs as shown in the following equation. Note that for capacitively−coupled inputs there is no offset voltage capable of producing a gain error. The only error will come from the bias current of the rectifier (supplied internally) which is less than 0.1 mA.

G T

* V

|avg

REF

|avg

G T

The speed with which gain changes to follow changes in input signal levels is determined by the rectifier filter capacitor. A small capacitor will yield rapid response but will not fully filter low frequency signals. Any ripple on the gain control signal will modulate the signal passing through the variable gain cell. In an expander or compressor application, this would lead to third harmonic distortion, so there is a trade−off to be made between fast attack and decay times and distortion. For step changes in amplitude, the change in gain with time is shown by this equation.

G(t) + (G

initial

t + 10kW C

* G

final

RECT

) G

final

The variable gain cell is a current−in, current−out device with the ratio I

OUT/IIN

controlled by the rectifier. IIN is the current which flows from the DG input to an internal summing node biased at V

. The following equation

REF

applies for capacitively−coupled inputs. The output current, I

, is fed to the summing node of the op amp.

OUT

* V

REF

A compensation scheme built into the DG cell

compensates for temperature and cancels out odd harmonic

distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset voltages. The THD trim terminal provides a means for nulling the internal offsets for low distortion operation.

The operational amplifier (which is internally

compensated) has the non−inverting input tied to V

REF

, and the inverting input connected to the DG cell output as well as brought out externally. A resistor , R3, is brought out from the summing node and allows compressor or expander gain to be determined only by internal components.

The output stage is capable of ±20 mA output current.

This allows a +13 dBm (3.5 V

) output into a 300 W load

RMS

which, with a series resistor and proper transformer, can result in +13 dBm with a 600 W output impedance.

A bandgap reference provides the reference voltage for all summing nodes, a regulated supply voltage for the rectifier and DG cell, and a bias current for the DG cell. The low tempco of this type of reference provides very stable biasing over a wide temperature range.

The typical performance characteristics illustration shows the basic input−output transfer curve for basic compressor or expander circuits.

+20 +10

−10

−20

−30

−40

−50

−60

−70

−80

−40 −30 −20 −10 0 +10

COMPRESSOR OUTPUT LEVEL

COMPRESSOR INPUT LEVEL OR EXPANDOR OUTPUT LEVEL (dBm)

EXPANDOR INPUT LEVEL (dBm)

Figure 2. Basic Input−Output Transfer Curve

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