ON Semiconductor NCV7428 User Manual

NCV7428

System Basis Chip with Integrated LIN and Voltage Regulator

Description

NCV7428 is a System Basis Chip (SBC) integrating functions typically found in automotive Electronic Control Units (ECUs). NCV7428 provides and monitors the low−voltage power supply for the application microcontroller and other loads and includes a LIN transceiver.

Features

• Control Logic

♦ Ensures safe power−up sequence and the correct reaction to

different supply conditions

♦ Controls mode transitions including the power management and

bus wakeup treatment

♦ Generates reset

• 3.3 V or 5 V V

Low−drop Voltage Regulator

♦ Can deliver up to 70 mA with accuracy of ±2% ♦ Supplies typically the ECU’s microcontroller ♦ Undervoltage detector with a reset output to the supplied

microcontroller

• LIN Transceiver

♦ LIN2.x and J2602 compliant ♦ TxD dominant timeout protection ♦ Transceiver mode controlled by dedicated input pin

• Protection and Monitoring Functions

♦ Thermal shutdown protection ♦ Load dump protection (45 V) ♦ LIN Bus pin protected against transients in an automotive

environment

♦ ESD protection level for LIN and V

• Wettable Flank Package for Enhanced Optical Inspection

Quality

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• Automotive

• Industrial Networks

Supply depending on the Version from a

OUT

> ±8 kV

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SOIC−8

D SUFFIX

CASE 751AZ

MARKING DIAGRAMS

NV7428xx

ALYW G

A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

PIN ASSIGNMENT

GND

LIN

ORDERING INFORMATION

See detailed ordering, marking and shipping information in the package dimensions section on page 17 of this data sheet.

NCV7428

(Top View)

DFN8

MW SUFFIX

CASE 506DG

NV7428xx

ALYWG

OUT

RSTN

TxD

RxD

November, 2018 − Rev. 7

1 Publication Order Number:

NCV7428/D

NCV7428

Block Diagram

RSTN

RxD

OUT

NCV7428

V−regREF

OUT

Control Logic

OUT

Wakeup

Detection

LIN Wakeup

LIN Active

OSC

OUT

Undervoltage

Receiver

Detection

Thermal

Shutdown

LIN

OUT

Driver &

Slope

TxD

Timeout

Control

GND

Figure 1. Block Diagram

Table 1. PIN DESCRIPTION

Pin Number Pin Name Pin Type Pin Function

1 V

2 EN LV LIN enable input;

3 GND Ground connection Ground connection

4 LIN LIN bus interface LIN bus line

5 RxD LV digital output; push−pull Output of data received on LIN bus

6 TxD LV digital input; internal pull−up Input of the data to be transmitted from LIN bus

7 RSTN LV digital output;

8 V

EP EP Exposed Pad Connect to GND or leave floating

NOTE: (LV = Low Voltage; HV = High Voltage)

OUT

Battery supply input Principle power supply of the device

Input of the LIN block enable signal

internal pull−down

System reset

open drain; internal pull−up

LV supply output Output of the 5 V or 3.3 V/70 mA low−drop regulator (for the MCU)

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NCV7428

Application Information

VBAT

LIN

GND

REV

PU_LIN

LIN_M

LIN

GND

OUT

RSTN

TxD

NCV7428

RxD

ECU1

PU_RSTN

VOUT

(MASTER)

MCU

GND

KL30

LIN−BUS

KL31

VBAT

LIN

GND

REV

PU_RSTN

OUT

RSTN

LIN

LIN_S

TxD

NCV7428

RxD

GND

ECU2

VOUT

(SLAVE)

MCU

GND

Figure 2. Example Application Diagram

External Components

Overview of external components from application schematic in Figure 2 is given in Table 2 together with their recommended or required values.

Table 2. EXTERNAL COMPONENTS OVERVIEW

Component

Name

REV

VOUT

PU_LIN

LIN_M

LIN_S

PU_RSTN

Reverse polarity protection diode parameters application−specific;

Filtering capacitor for the battery input recommended >100 nF ceramic

Voltage regulator output filtering and

Master node Pull−up diode on LIN line

Master node Pull−up resistor on LIN line

Filtering capacitor on LIN line (Master node) typically 1 nF optional; is function of the

Filtering capacitor on LIN line (Slave node) typically 100 pF – 220 pF optional; is function of the

Pull−up resistor at RSTN pin

Description Value Note

stabilization capacitor

e.g. 0.5 A / 50 V

> 1.8 mF, ESR < 7 W

1 kW nominal, ≥500 mW

recommended 10 kW nominal

required values and types

depend on the V

and the application needs

OUT

load

required only for master

LIN node

entire LIN network

optional; depends on

application needs

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NCV7428

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Units

OUT

LIN

Dig_IO_inputs

Dig_IO_outputs

AMB

STG

ESD

MSL Moisture Sensitivity Level SOIC

SLD

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Maximum DC voltage at VS pin −0.3 45 V

Maximum voltage at V

pin −0.3 6 V

OUT

Maximum voltage at LIN bus pin −45 45 V

Maximum voltage at digital input pins (TxD, EN) −0.3 45 V

Maximum voltage at digital output pins (RxD, RSTN) −0.3 V

+0.3 V

OUT

Ambient temperature range −40 +125 °C

Junction temperature range −40 +170 °C

Storage temperature range −55 +150 °C

System ESD at pins VS, LIN as per IEC 61000−4−2: 330 W / 150 pF

≥ ±14

(Verified by external test house)

Human body model at pins VS, LIN stressed towards GND with 1500 W / 100 pF ≥ ±8

Human body model at all pins as per JESD22−A114 / AEC−Q100−002

Charge device model at all pins as per JESD22−C101 / AEC−Q100−011

Machine model; (200 pF; 0.75 mH; 10 W) as per JESD22−A115 / AEC−Q100−003

≥ ±4

≥ ±500

±200 V

DFN

Lead temperature Soldering − Reflow (SMD styles only), Pb−Free (Note 1) 260 °C

−

Table 4. OPERATING RANGES

Symbol Parameter Min Max Units

VS operating voltage for parametric operation (Note 2) 5.5 28 V

VS operating voltage for limited operation (Note 2) 4 28 V

OUT5

OUT33

VOUT

LIN

Dig_IO_inputs

Dig_IO_outputs

Regulated voltage at V

Current delivered by the V

Operating voltage at LIN bus pin 0 V

supply output for 5 V versions 4.9 5.1 V

OUT

supply output for 3.3 V versions 3.234 3.366 V

OUT

regulator 70 mA

OUT

Operating voltage at digital input pins (TxD, EN) 0 5.5 V

Operating voltage at digital output pins (RxD, RSTN) 0 V

OUT

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

2. Below 5.5 V at V

specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. Above 28 V at V operational (LIN pin toggling) but parameters cannot be guaranteed. For higher battery voltage operation above 28 V, LIN pull−up resistor

pin in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time

pin, LIN communication is

must be selected large enough to avoid clamping of LIN pin by voltage drop over external pull−up resistor and LIN pin min current limitation.

Table 5. THERMAL CHARACTERISTICS

Rating Symbol Value Unit

Thermal Characteristics, SOIC−8 (Note 3)

Thermal Characteristics, DFN−8 (Note 3)

3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

4. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.

5. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage for the signal layer and

4 thermal vias connected between exposed pad and first inner Cu layer.

Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4) Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)

125

133

°C/W °C/W

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NCV7428

Definitions

The characteristics defined in this section are guaranteed within the operating ranges listed in Table 4, unless stated otherwise. All voltages are referenced to GND (Pin 3). Positive currents flow into the respective pin.

Table 6. DC CHARACTERISTICS (V

specified. Typical values are given at V

Symbol

Parameter Conditions Min Typ Max Unit

= 5.5 V to 28 V; TJ = −40°C to +150°C; Bus Load = 500 W (VS to LIN); unless otherwise

= 12 V and TJ = 25°C, unless otherwise specified.)

SUPPLY MONITORING

S_PORH

S_PORL

OUT_RES_5

OUT_RES_33

OUT_RES_hys5

OUT_RES_hys33VOUT

VS threshold for the power−up of the circuit

VS threshold for the Shutdown of the circuit

monitoring threshold

OUT

NV7428−5

monitoring threshold

OUT

NV7428−3

monitoring threshold

OUT

hysteresis for NV7428−5

monitoring threshold

hysteresis for NV7428−3

VS rising 3.3 4 V

VS falling 2.2 3 V

falling 4.55 4.75 V

OUT

falling 2.97 3.135 V

OUT

0.1 V

0.06 V

CURRENT CONSUMPTION

VS_LIN_Active_recVS

VS_LIN_Wakeup

VS_Sleep

REGULATOR

OUT

OUT_5

OUT_33

OUT_5_EMC

supply current LIN Active, LIN bus recessive 1.8 mA

VS supply current (Note 8) Standby mode; LIN Wakeup,

LIN bus recessive; I VS = 13.5 V, TJ < 105°C

VOUT

= 0 mA

VS supply current (Note 8) Sleep mode; LIN Wakeup, LIN bus

regulator output voltage

OUT

(Note 6)

regulator output voltage

OUT

(Note 6)

regulator output voltage

OUT

under EMC (Note 8)

recessive; V VS = 13.5 V, TJ < 105°C

regulator active,

OUT

0 < I

VOUT

regulation, VS = 5.5 V to 28 V

regulator active,

OUT

0 < I

VOUT

regulation, V

DPI EMC test applied to LIN pin. No bus capacitor. SOIC8 package;

off, V

OUT

< 70 mA, Static

= 4.5 V to 28 V

< 0.5 V

4.9 5 5.1 V

3.234 3.3 3.366 V

4.85 5 5.15 V

25 33

12 18

(Note 7)

OUT_33_EMC

regulator output voltage

OUT

under EMC (Note 8)

DPI EMC test applied to LIN pin. No bus capacitor. SOIC8 package;

3.201 3.3 3.399 V

(Note 7)

LIM_VOUT

DROP_VOUT

SINK_VOUT

VOUT

current limitation V

OUT

Drop−out voltage between V and V

OUT

sink current V

OUT

regulator filtering

OUT

capacitance (Note 9)

regulator active;

OUT

current flowing to V

5.5 V < VS < 40 V;

= 70 mA

VOUT

regulator active, current

OUT

flowing into the V

Equivalent series resistance < 7 W

OUT

load

70 120 350 mA

0.55 V

100 240 400

1.8 10

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. In case LIN bus capacitor of at least 82 pF is not used V

7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10

OUT_5_EMC

and V

OUT_33_EMC

needs to be taken into account.

th, 2008. Verified by external test house.

8. Values based on design and characterization. Not tested in production.

9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value

10.The voltage drop in Normal mode between LIN and V at the switch is negligible. See Figure 1.

pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop

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NCV7428

Table 6. DC CHARACTERISTICS (V

specified. Typical values are given at V

= 5.5 V to 28 V; TJ = −40°C to +150°C; Bus Load = 500 W (VS to LIN); unless otherwise

= 12 V and TJ = 25°C, unless otherwise specified.)

Symbol UnitMaxTypMinConditionsParameter

LIN TRANSMITTER

LIN_dom_LoSup

LIN_dom_HiSup

LIN_REC

LIN_lim

slave

LIN

LIN dominant output voltage TxD = Low; VS = 7.3 V 1.2 V

LIN dominant output voltage TxD = Low; VS = 18 V 2.0 V

LIN recessive output voltage

Short circuit current limitation V

TxD = High; I

= VS = 18 V 40 200 mA

LIN

= 10 mA (Note 10)

LIN

Internal Pull−up Resistance LIN Normal or Receive−only mode 20 33 47

VS – 1.5 V

Capacitance at pin LIN (Note 8) 20 30 pF

LIN Receiver

bus_dom

bus_rec

rec_dom

rec_rec

rec_cnt

rec_hys

LIN_off_dom

LIN_off_dom_wake

LIN_off_rec

LIN_no_GND

LIN_no_VBB

Bus voltage for Dominant state 0.4 V

Bus voltage for Recessive state 0.6 V

Receiver threshold LIN bus going from Recessive to

0.4 0.6 V

Dominant

Receiver threshold LIN bus going from Dominant to

0.4 0.6 V

Recessive

Receiver center voltage (V

Receiver hysteresis V

LIN output current, Bus in dominant state

LIN output current, Bus in recessive state

LIN Active Mode, Driver Off; V

LIN Wakeup Mode; V

Driver Off; VS < 18 V; V

LIN current with missing GND VS = GND = 12 V; 0 < V

LIN current with missing V

VS = GND = 0 V; 0 < V

rec_dom

rec_rec

= 12 V, V

< V

LIN

+ V

− V

< 18 V

)/2 0.475 0.525 V

rec_rec

rec_dom

0.05 0.175 V

−1 mA

= 0 V

LIN

−20 −15 −2

= 0 V

LIN

< 18 V −1 1 mA

LIN

< 18 V 5

LIN

PIN EN

IL_EN

IH_EN

pulldown_EN

Low−level input voltage −0.3 0.8 V

High−level input voltage 2 5.5 V

Pull−down resistance to GND 55 100 185

PIN TxD

IL_TxD

IH_TxD

pullup_TxD

leak_TxD

Low−level input voltage −0.3 0.8 V

High−level input voltage 2 5.5 V

Pull−up resistance to V

OUT

Leakage current V

TxD

= V

= 5.5 V −1 0 1

OUT

55 100 185

PIN RSTN

OL_RSTN

pullup_RSTN

Low−level output driving current VS = 4 V to 28 V; V

Low−level output voltage

Pull−up resistance to V

OUT

VS = 2 V to 4 V; V

5.5 V; I

VS < 2 V; V I

RSTN

= 100 mA

RSTN

OUT

= 100 mA

= 1 V to 5.5 V;

= 0.4 V 4 30 mA

RSTN

= 0 V to

OUT

55 100 185

0.1 V

OUT

6. In case LIN bus capacitor of at least 82 pF is not used V

7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10

OUT_5_EMC

and V

OUT_33_EMC

needs to be taken into account.

th, 2008. Verified by external test house.

8. Values based on design and characterization. Not tested in production.

9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value

10.The voltage drop in Normal mode between LIN and V at the switch is negligible. See Figure 1.

pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop

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