ON Semiconductor NCP51820 User manual

High Speed Half-Bridge Driver for GaN Power Switches

NCP51820

The NCP51820 high−speed, gate driver is designed to meet the stringent requirements of driving enhancement mode (e−mode), high electron mobility transistor (HEMT) and gate injection transistor (GIT), gallium nitrade (GaN) power switches in off−line, half−bridge power topologies. The NCP51820 offers short and matched propagation delays with advanced level shift technology providing

−3.5 V to +650 V (typical) common mode voltage range for the high−side drive and −3.5 V to +3.5 V common mode voltage range for the low−side drive. In addition, the device provides stable dV/dt operation rated up to 200 V/ns for both driver output stages in high speed switching applications.

To fully protect the gate of the GaN power transistor against excessive voltage stress, both drive stages employ a dedicated voltage regulator to accurately maintain the gate−source drive signal amplitude. The circuit actively regulates the driver’s bias rails and thus protects against potential gate−source over−voltage under various operating conditions.

The NCP51820 offers important protection functions such as independent under−voltage lockout (UVLO), monitoring VDD bias voltage and VDDH and VDDL driver bias and thermal shutdown based on die junction temperature of the device. Programmable dead−time control can be configured to prevent cross−conduction.

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QFN15 4x4, 0.5P

CASE 485FN

MARKING DIAGRAM

51820A ALYW G

G

51820A = Specific Device Code A = Assembly Site L = Wafer Lot Number YW = Assembly Start Week G = Pb−Free Package

(Note: Microdot may be in either location)

Features

• 650 V, Integrated High−Side and Low−Side Gate Drivers

• UVLO Protections for VDD High and Low−Side Drivers

• Dual TTL Compatible Schmitt Trigger Inputs

• Split Output Allows Independent Turn−ON/Turn−OFF Adjustment

• Source Capability: 1 A; Sink Capability: 2 A

• Separated HO and LO Driver Output Stages

• 1 ns Rise and Fall Times Optimized for GaN Devices

• SW and PGND: Negative Voltage Transient up to 3.5 V

• 200 V/ns dV/dt Rating for all SW and PGND Referenced Circuitry

• Maximum Propagation Delay of Less Than 50 ns

• Matched Propagation Delays to Less Than 5 ns

• User Programmable Dead−Time Control

• Thermal Shutdown (TSD)

Typical Applications

• Driving GaN Power Transistors used in Full or Half−Bridge, LLC,

Active Clamp Flyback or Forward, Totem Pole PFC and Synchronous Rectifier Topologies

• Industrial Inverters and Motor Drives

• AC to DC Converters

PIN ASSIGNMENT

VBST

15

VDDH

HOSRC

HOSNK

NCP51820AMNTWG QFN15

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

1

2

3

SW

4

ORDERING INFORMATION

Device Package Shipping

NCP51820

(Top View)

5

6

VDDL

LOSRC

(Pb−Free)

VDD8

14

7

PGND

LOSNK

13

EN

HIN

12

LIN

11

SGND

10

DT

9

4000 / Tape

& Reel

†

February, 2021 − Rev. 3

1 Publication Order Number:

NCP51820/D

NCP51820

VDDVIN

VBST

POWER

STAGE

VBST

15

VDDH

1

HOSRC

2

HOSNK

SW

3

4

NCP51820

(Top View)

5

VDDL

6

LOSRC

7

LOSNK

Figure 1. Typical Application Schematic

VDD

14

13

12

11

10

9

8

PGND

VDDH

REGULATOR

EN

HIN

LIN

SGND

DT

PWM

mC

or

DSP

VDDH

VDD

EN

HIN

LIN

DT

SGND

VDD

UVLO

8.5V/8V

(ON/OFF)

SCHMITT

TRIGGER INPUT

SHOOT THOUGH

PREVENTION

CYCLE−By−

CYCLE EDGE

TRIGGERED SHUTDOWN

DEAD−TIME

MODE CONTROL

HO

LEVEL SHIFTER

LO

LEVEL SHIFTER

S

Q

R

VDDL

REGULATOR

VDDL UVLO

DELAY

Figure 2. Internal Block Diagram

VDDH UVLO

DRIVER

HOSRC

HOSNK

SW

VDDL

LOSRC

LOSNK

PGND

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PIN CONNECTIONS

NCP51820

VDDH

HOSRC

HOSNK

SW

VBST

15

1

2

3

4

NCP51820

(Top View)

5

6

VDDL

LOSRC

7

LOSNK

VDD8

14

PGND

Figure 3. Pin Assignments – 15 Lead QFN (Top View)

PIN DESCRIPTION

Pin No. Name Description

1 VDDH High−side driver positive bias voltage output

2 HOSRC High−side driver sourcing output

3 HOSNK High−side driver sinking output

4 SW Switch−node / high−side driver return

5 VDDL Low−side driver positive bias voltage output

6 LOSRC Low−side driver sourcing output

7 LOSNK Low−side driver sinking output

8 PGND Power ground / low−side driver return

9 DT Dead time adjustment / mode select

10 SGND Logic / signal ground

11 LIN Logic input for low−side gate driver output

12 HIN Logic input for high−side gate driver output

13 EN Logic input for disabling the driver (low power mode)

14 VDD Bias voltage for high current driver

15 VBST Bootstrap positive bias voltage

13

12

11

10

EN

HIN

LIN

SGND

9

DT

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NCP51820

ABSOLUTE MAXIMUM RATINGS (All voltages are referenced to SGND pin unless otherwise noted)

Symbol

V

DD

V

DDL

V

SW

V

DDH

V

BST_SGND

V

BST_SW

V

HOSRC

V

HOSNK

V

PGND

V

LOSRC

V

LOSNK

V

IN

V

DT

Low−side and logic−fixed supply voltage (PGND = SGND) −0.3 20 V

Low−side supply voltage V connect to external voltage source, referenced to PGND)

High−side common mode voltage range (SW) −3.5 650 V

High−side floating supply voltage V do not connect to external voltage source; referenced to SW)

High−side floating supply voltage V

,

High−side floating driver sourcing/sinking output voltage (referenced to SW) −0.3 V

PGND voltage −3.5 3.5 V

,

Low−side driver sourcing/sinking output voltage (referenced to PGND) −0.3 V

Logic input voltage (HIN, LIN, and EN) −0.3 VDD+0.3 V

Dead−time control voltage (DT) −0.3 VDD+0.3 V

dVSW/dt Allowable offset voltage slew rate − 200 V/ns

T

STG

Operating Junction Temperature − 150 °C

J

Storage Temperature Range −55 150 °C

Electrostatic Discharge Capability

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

– PGND voltage must not exceed 20 V

2. V

DD

3. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012 ESD Charged Device Model tested per JESD22−C101.

4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 Class I.

Rating Min Max Unit

(internally regulated; output only, do not

DDL

(internally regulated; output only,

DDH

BST

(referenced to SW) −0.3 20 V

BST

−0.3 5.5 V

−0.3 670 V

DDH

DDL

Human Body Model (Note 3) − 1 kV

Charged Device Model (Note 3) − 1 kV

+0.3 V

THERMAL CHARACTERISTICS

Symbol Rating Value Unit

q

JA

P

Thermal Characteristics, QFN15 4x4 (Note 5) Thermal Resistance Junction−Ambient (Note 6)

Power Dissipation (Note 6)

D

QFN15 4x4 (Note 5)

IS0P 245

IS2P 188

IS0P 0.51

IS2P 0.665

°C/W

W

5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

6. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2×114.3×1.6 mm PCB (FR−4 glass epoxy material).

IS0P: one single layer with zero power planes IS2P: one single layer with two power planes

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NCP51820

RECOMMENDED OPERATING CONDITIONS (All voltages are referenced to SGND pin unless otherwise noted)

Symbol

V

DD

Low−side and logic−fixed supply voltage 9 17 V

VSW−SGND SW−SGND maximum dc offset voltage (High−Side driver) − 580 V

V

HOSRC

V

LOSRC

V

BST

, V

HOSNK

, V

LOSNK

V

IN

High−side floating supply voltage V

High−side floating driver sourcing/sinking output voltage − V

Low−side driver sourcing/sinking output voltage − V

Logic input voltage (HIN, LIN, and EN) − 17 V

PGND−SGND PGND−SGND maximum dc offset voltage (Low−Side driver) −3.0 3.0 V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

Rating Min Max Unit

BST

− VSW+17 V

DDH

DDL

V

ELECTRICAL CHARACTERISTICS (V

T

= 25°C, for min/max values T

A

The V

and IO parameters are referenced to VSW and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC,

O

= −40°C to +125°C, unless otherwise specified.) The V

A

BIAS

(VDD, V

) = 15 V, DT = SGND = PGND and C

BST

and IIN parameters are referenced to SGND.

IN

= 330 pF for typical values

LOAD

and LOSNK.

Symbol

Parameter Test Conditions and Description Min Typ Max Unit

POWER SUPPLY SECTION (VDD)

I

QDD

I

PDD

V

DDUV+

V

DDUV−

V

DDHYS

t

UVDDFLT

Quiescent VDD supply current V

Operating VDD supply current f

VDD UVLO positive going threshold V

VDD UVLO negative going threshold V

VDD UVLO Hysteresis V

VDD UVLO Filter Delay Time (Note 7) − 5.3 −

= V

LIN

DD

= 0 V, EN = 0 V − 100 150

HIN

= 500 kHz, average value − 1.5 2.5 mA

= Sweep 8.0 8.5 9.0 V

= Sweep 7.5 8.0 8.5 V

= Sweep − 0.5 − V

BOOTSTRAPPED POWER SUPPLY SECTION

I

LK

I

QBST

I

PBST

V

BSTUV+

V

BSTUV−

V

HYST

Offset supply leakage current V

Quiescent V

Operating V

V

UVLO positive going threshold V

BST

V

UVLO negative going threshold V

BST

V

UVLO Hysteresis V

BST

supply current V

BST

supply current f

BST

LIN

HIN

DD

= V

= 600 V − − 10

SW

= V

= 0 V, EN = 5 V − 35 100

HIN

= 500 kHz, average value − 1.5 2.5 mA

= 12 V − 6.5 − V

= 12 V − 6.0 − V

= 12 V − 0.5 − V

GATE DRIVER POWER SUPPLY SECTION

V

DDH

DDL

V

DDH−VSW

V

DDL

regulated voltage

−PGND regulated voltage 4.94 5.20 5.46 V

0 mA < IO < 10 mA

4.94 5.20 5.46 V

INPUT LOGIC SECTION (HIN, LIN and EN)

V

IN_HYS

I

IN+

I

IN−

R

INH

INL

IN

High Level Input Voltage Threshold − − 2.5 V

Low Level Input Voltage Threshold 1.2 − − V

Input Logic Voltage Hysteresis − 0.5 − V

High Level Logic Input Bias Current V

Low Level Logic Input Bias Current V

Input Pull−down Resistance V

HIN

= V

= 5 V 9 15 21

LIN

= V

= 0 V − − 2.2

LIN

= V

= 5 V − 333 −

LIN

DEAD−TIME SECTION

V

DT,MIN

t

DT,MIN

Minimum Dead−Time Control Voltage

R

= 30 kW 0.45 0.60 0.75 V

DT

22 30 38 ns

mA

ms

mA

kW

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NCP51820

ELECTRICAL CHARACTERISTICS (V

T

= 25°C, for min/max values T

A

The V

and IO parameters are referenced to VSW and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC,

O

= −40°C to +125°C, unless otherwise specified.) The V

A

BIAS

(VDD, V

) = 15 V, DT = SGND = PGND and C

BST

and IIN parameters are referenced to SGND.

IN

= 330 pF for typical values

LOAD

and LOSNK. (continued)

Symbol UnitMaxTypMinTest Conditions and DescriptionParameter

DEAD−TIME SECTION

V

DT,MAX

t

DT,MAX

Dt

V

DT,0

V

DT,OLE

DT

Maximum Dead−Time Control Voltage

Dead−Time mismatch between LO → HO and HO → LO

Dead−Time Disable Threshold Cross conduction prevention active 0.35 0.40 0.45 V

High− & Low−Side Overlap Enable Threshold

R

= 200 kW 3.1 4.0 4.8 V

DT

160 200 240 ns

R

= 30 kW

DT

R

= 200 kW

DT

Cross conduction prevention

− − 5 ns

− − 10 ns

5.5 6.0 6.5 V

disabled

PROTECTION SECTION

V

UVTH_VDDX+

V

UVTH_VDDX−

UVLO Threshold on VDDH and VDDL positive going threshold

UVLO Threshold on VDDH and VDDL negative going threshold

4.15 4.40 4.70 V

4.0 4.2 4.5 V

TSD Thermal Shutdown (Note 7) 150 − − °C

hys Hysteresis of Thermal Shutdown

− 50 − °C

(Note 7)

GATE DRIVE OUTPUT SECTION

V

OH

V

OL

I

OSRC

I

OSNK

High−level output voltage, V

VDDH−VHOSRC

or V

VDDL−VLOSRC

Low−level output voltage, V

HOSNK−VSW

or V

LOSNK

–PGND

Peak source current (Note 7)

Peak sink current (Note 7)

I

= 10 mA − 10 40 mV

OSRC

I

= 10 mA − 5 20 mV

OSNK

C

LOAD

C

LOAD

= 200 pF, R

gate

= 1 W

0.9 1.0 − A

1.8 2.0 − A

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Guaranteed by design, is not tested in production.

DYNAMIC ELECTRICAL CHARACTERISTICS (V

values T

Symbol

t

=25°C, for min/max values TA=−40°C to +125°C, unless otherwise specified.) (Notes 9)

A

Parameter Test Conditions Min Typ Max Unit

I

QDD

t

PDLON

t

PDLOFF

t

PDHON

PDHOFF

t

RL

t

FL

t

RH

t

FH

Quiescent VDD supply current V

LOSRC turn−on propagation delay

LIN rising to LOSRC rising (50% to 10%) − 25 50 ns

time

LOSNK turn−off propagation delay

LIN falling to LOSNK falling (50% to 90%) − 25 50 ns

time

HOSRC turn−on propagation delay time

HOSNK turn−off propagation delay time

HIN rising to HOSRC rising (50% to 10%) SW = PGND

HIN falling to HOSNK falling (50% to 90%) SW = PGND

LOSRC turn−on rising time − 2 4 ns

LOSNK turn−off falling time − 1.5 3.0 ns

HOSRC turn−on rising time

SW = PGND

HOSNK turn−off falling time − 1.5 3.0 ns

(VDD, V

LIN

BIAS

= V

BST

= 0 V, EN = 0 V − 100 150

HIN

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)=15 V, DT=SGND=PGND and C

− 25 50 ns

− 2 4 ns

=330 pF, for typical

LOAD

mA

NCP51820

DYNAMIC ELECTRICAL CHARACTERISTICS (V

values T

=25°C, for min/max values TA=−40°C to +125°C, unless otherwise specified.) (Notes 9) (continued)

A

BIAS

(VDD, V

)=15 V, DT=SGND=PGND and C

BST

=330 pF, for typical

LOAD

Symbol UnitMaxTypMinTest ConditionsParameter

Dt

DEL

t

PW

Propagation Delay match HIN to HO and LIN to LO, SW = PGND − − 5 ns

Minimum input pulse width − − 10 ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. This parameter, although guaranteed by design, is not tested in production.

9. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T

= TA = 25°C.

J

Timing Diagram

Shown in Figure 4 are the timing waveform definitions matching the specified dynamic electrical characteristics specified in the gate drive output section.

50%

HIN

(LIN)

90%

10%

HO

(LO)

t

PDHON

(t

PDLON

Figure 4. Input to Output Timing Diagram

)

t

RH

(tRL)

t

PDHOFF

(t

PDLOFF

t

FH

)

(tFL)

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