Designed for general purpose power and switching such as output or
driver stages in applications such as switching regulators, converters,
and power amplifiers.
Features
• Lead Formed for Surface Mount Applications in Plastic Sleeves
(No Suffix)
• Straight Lead Version in Plastic Sleeves (“−1” Suffix)
• Electrically Similar to Popular TIP31 and TIP32 Series
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
R
q
JC
R
q
JA
100Vdc
100Vdc
5Vdc
2
4
50mAdc
20
0.16
1.75
0.014
−65 to + 150°C
6.25°C/W
71.4°C/W
Adc
W
W/°C
W
W/°C
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SILICON
POWER TRANSISTORS
2 AMPERES
100 VOLTS, 20 WATTS
MARKING
DIAGRAMS
4
YWW
2
1
3
DPAK
CASE 369C
4
1
2
3
DPAK−3
CASE 369D
Y= Year
WW= Work Week
x= 2 or 7
G= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
*These ratings are applicable when surface mounted on the minimum pad sizes recommended.
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
D1, MUST BE FAST RECOVERY TYPE, e.g.:
V
CC
−30 V
4
1N5825 USED ABOVE IB ≈ 100 mA
MSD6100 USED BELOW IB ≈ 100 mA
V
2
APPROX
+8 V
0
V
1
51
APPROX
−12 V
tr, tf ≤ 10 ns
DUTY CYCLE = 1%
25 ms
FOR td AND tr, D1 IS DISCONNECTED
AND V2 = 0
FOR NPN TEST CIRCUIT REVERSE ALL POLARITIES.
R
D
B
1
+ 4 V
≈ 8 k
TUT
≈ 60
R
C
SCOPE
2
1
0.8
t, TIME (s)μ
0.6
0.4
0.2
0.040.240.1
PNP
NPN
0.06
IC, COLLECTOR CURRENT (AMP)
ÎÎ
−
Î
2.8
Vdc
ÎÎ
MHz
25
ÎÎ
−
Î
ÎÎ
pF
−
ÎÎ
−
VCC = 30 V
t
s
IC/IB = 250
0.42
200
Î
100
0.61
t
f
td @ V
ÎÎ
IB1 = I
B2
TJ = 25°C
t
= 0 V
BE(off)
r
Figure 1. Switching Times Test CircuitFigure 2. Switching Times
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2
1
ACTIVE−REGION SAFE−OPERATING AREA
0.7
0.5
0.3
0.2
0.1
0.07
0.05
r(t), EFFECTIVE TRANSIENT
0.03
0.02
THERMAL RESISTANCE (NORMALIZED)
0.01
0.01
10
7
5
3
2
1
0.7
0.5
0.3
0.2
0.1
, COLLECTOR CURRENT (AMP)
C
I
2
MJD112 (NPN) MJD117 (PNP)
D = 0.5
0.2
0.1
0.05
0.01
SINGLE PULSE
0.02 0.03 0.050.10.2 0.30.5123510203050100200 300500
t, TIME OR PULSE WIDTH (ms)
R
= r(t) R
q
JC(t)
R
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
J(pk)
q
= 6.25°C/W
− TC = P
(pk) qJC(t)
JC
1
Figure 3. Thermal Response
TAT
C
25
2.5
100ms
500ms
1ms
BONDING WIRE LIMITED
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
TJ = 150°C
CURVES APPLY BELOW RATED V
5203
10730
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
5ms
dc
CEO
50 70200
100
1.5
0.5
, POWER DISSIPATION (WATTS)
D
P
20
2
15
10
1
5
0
0
25
SURFACE
MOUNT
507510012515
P
(pk)
t
1
DUTY CYCLE, D = t1/t
T
TA
T, TEMPERATURE (°C)
C
t
2
2
1000
Figure 4. Maximum Rated Forward Biased
Safe Operating Area
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
limits of the transistor that must be observed for reliable
C
− V
CE
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figures 5 and 6 is based on T
= 150_C; T
J(pk)
is variable depending on conditions. Second breakdown
pulse limits are valid for duty cycles to 10% provided
T
< 150_C. T
J(pk)
may be calculated from the data in
J(pk)
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
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Figure 5. Power Derating
200
100
70
C, CAPACITANCE (pF)
50
30
20
10
0.04
C
ib
PNP
NPN
0.12620
VR, REVERSE VOLTAGE (VOLTS)
141040
0.60.40.20.06
C
TC = 25°C
C
ob
Figure 6. Capacitance
3
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