Designed primarily for half–wave ac control applications, such as
motor controls, heating controls, and power supplies; or wherever
half–wave, silicon gate–controlled devices are needed.
• Blocking Voltage to 800 Volts
• On–State Current Rating of 12 Amperes RMS at 80°C
• High Surge Current Capability — 100 Amperes
• Rugged, Economical TO–220AB Package
• Glass Passivated Junctions for Reliability and Uniformity
• Minimum and Maximum Values of IGT, VGT and IH Specified for
Ease of Design
• High Immunity to dv/dt — 100 V/µsec Minimum at 125°C
• Device Marking: Logo, Device T ype, e.g., MCR12LD, Date Code
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SCRs
12 AMPERES RMS
400 thru 800 VOLTS
G
A
K
MAXIMUM RATINGS (T
Rating
Peak Repetitive Off–State V oltage
(TJ = –40 to 125°C, Sine Wave, 50 to
60 Hz, Gate Open)MCR12LD
On-State RMS Current
(180° Conduction Angles; TC = 80°C)
Peak Non-repetitive Surge Current
(1/2 Cycle, Sine Wave 60 Hz,
TJ = 125°C)
Circuit Fusing Consideration
(t = 8.3 ms)
Forward Peak Gate Power
(Pulse Width ≤ 1.0 µs, TC = 80°C)
Forward Average Gate Power
(t = 8.3 ms, TC = 80°C)
Forward Peak Gate Current
(Pulse Width ≤ 1.0 µs, TC = 80°C)
Operating Junction Temperature RangeT
Storage Temperature RangeT
(1) V
and V
DRM
apply for zero or negative gate voltage; positive gate voltage shall not be
applied concurrent with negative potential on the anode. Blocking voltages
shall not be tested with a constant current source such that the voltage
ratings of the devices are exceeded.
RRM
= 25°C unless otherwise noted)
J
SymbolValueUnit
(1)
MCR12LM
MCR12LN
for all types can be applied on a continuous basis. Ratings
Peak Repetitive Off State Forward Voltage
Peak Forward Blocking Current
Peak Repetitive Off State Reverse Voltage
Peak Reverse Blocking Current
Peak On State Voltage
Holding Current
TJ, JUNCTION TEMPERATURE (°C)
I
at V
RRM
Reverse Avalanche Region
Anode –
11050658095
RRM
Reverse Blocking Region
(off state)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
GT
V , GATE TRIGGER VOLTAGE (VOLTS)
0.2
V
TM
on state
I
H
Forward Blocking Region
TJ, JUNCTION TEMPERATURE (°C)
I
DRM
(off state)
at V
+ Voltage
DRM
11095806550355.0–40–10–2520
125
100
H
I , HOLDING CURRENT (mA)
Figure 1. T ypical Gate Trigger Current
versus Junction T emperature
10
1.0
–40
–25 –105.02035125
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Typical Holding Current
versus Junction T emperature
Figure 2. T ypical Gate Trigger Voltage
versus Junction T emperature
100
10
, LATCHING CURRENT (mA)
L
I
11050658095
1.0
–40
–25 –105.02035125
TJ, JUNCTION TEMPERATURE (°C)
11050658095
Figure 4. T ypical Latching Current
versus Junction T emperature
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3
MCR12LD, MCR12LM, MCR12LN
125
120
115
110
105
100
C
T , CASE TEMPERATURE ( C)°
95
90
046812
α = 30°
I
, RMS ON-STATE CURRENT (AMP)
T(RMS)
α = CONDUCTION ANGLE
60°
90°
180°
α
dc
10
11579123
Figure 5. Typical RMS Current Derating
100
70
50
30
20
18
16
α = CONDUCTION ANGLE
14
12
10
8
6
4
2
(AV)
0
P , AVERAGE POWER DISSIPATION (WATTS)
Figure 6. On–State Power Dissipation
α
α = 30°
I
, AVERAGE ON-STATE CURRENT (AMPS)
T(AV)
90°
180°
dc
TJ = 125°C
1004681211579123
20
10
7.0
5.0
3.0
2.0
1.0
T
I , INSTANTANEOUS ON–STATE CURRENT (AMPS)
0.7
0.5
0.3
0.2
0.1
125°C
25°C
0.5
1.0
VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)
1.52.02.53.0
Figure 7. T ypical On–State Characteristics
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4
MCR12LD, MCR12LM, MCR12LN
P ACKAGE DIMENSIONS
TO–220AB
CASE 221A–09
ISSUE Z
SEATING
–T–
PLANE
T
4
Q
123
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
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MCR12L/D
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