MC74HCT374A
f
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of Clock. The Output Enable does not affect the state of
the flip−flops, but when Output Enable is high, the outputs are forced
to the high−impedance state. Thus, data may be stored even when the
outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT534A, which has
inverting outputs.
Features
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 276 FETs or 69 Equivalent Gates
• Improvements over HCT374
♦ Improved Propagation Delays
♦ 50% Lower Quiescent Power
♦ Improved Input Noise and Latchup Immunity
• These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
2
Q0
5
Q1
6
Q2
9
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
12
15
16
19
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
CLOCK
3
4
7
8
13
14
17
18
11
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SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
20
OUTPUT ENABLE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
V
CC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
11
CLOCK
MARKING DIAGRAMS
20
HCT374A
AWLYYWWG
1
SOIC−20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
20
1
TSSOP−20
FUNCTION TABLE
Inputs Output
Output
Enable Clock D Q
LHH
LLL
L L,H, X No Change
HXXZ
X = don’t care
Z = high impedance
HCT
374A
ALYWG
G
OUTPUT ENABLE
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 12
1
PIN 20 = V
PIN 10 = GND
CC
See detailed ordering and shipping information on page 5 o
ORDERING INFORMATION
this data sheet.
1 Publication Order Number:
MC74HCT374A/D
MC74HCT374A
Design Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
Value
69
1.5
5.0
.0075
Units
ea.
ns
mW
pJ
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
T
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
CC
V
DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
in
DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
out
I
DC Input Current, per Pin ±20 mA
in
I
DC Output Current, per Pin ±35 mA
out
I
DC Supply Current, VCC and GND Pins ±75 mA
CC
P
Power Dissipation in Still Air, SOIC Package†
D
TSSOP Package†
Storage Temperature –65 to +150
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
(SOIC or TSSOP Package)
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
500
450
260
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, V
V
should be constrained to the
out
range GND v (V
or V
in
) v VCC.
out
in
and
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
Unused outputs must be left open.
).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
Vin, V
tr, tfInput Rise and Fall Time (Figure 1) 0 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
CC
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
out
T
Operating Temperature, All Package Types –55 +125
A
CC
V
_C
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MC74HCT374A
l
l
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
V
Minimum High−Level Input Voltage V
IH
V
Maximum Low−Level Input Voltage V
IL
V
V
Minimum High−Level Output Voltage
OH
Maximum Low−Level Output Voltage
OL
I
Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0
in
I
Maximum Three−State Leakage
OZ
Current
I
Maximum Quiescent Supply Current
CC
(per Package)
DI
Additional Quiescent Supply Current Vin = 2.4 V, Any One Input
CC
1. Total Supply Current = ICC + ΣDICC.
Parameter Test Conditions
= 0.1 V or VCC – 0.1 V
out
|I
| ≤ 20 mA
out
= 0.1 V or VCC – 0.1 V
out
|I
| ≤ 20 mA
out
Vin = VIH or V
|I
| ≤ 20 mA
out
Vin = VIH or V
|I
| ≤ 6.0 mA 4.5 3.98 3.84 3.7
out
Vin = VIH or V
|I
| ≤ 20 mA
out
Vin = VIH or V
|I
| ≤ 6.0 mA 4.5 0.26 0.33 0.4
out
IL
IL
IL
IL
Output in High−Impedance State
= VIL or V
V
in
V
= VCC or GND
out
IH
Vin = VCC or GND
I
= 0 mA
out
V
= VCC or GND, Other Inputs
in
= 0 mA
l
out
Guaranteed Limit
CC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
−55 to
25_C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
≤ 85_C ≤ 125_C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
V
5.5 ±0.5 ±5.0 ±10
5.5 4.0 40 160
≥ −55_C 25_C to 125_C
5.5
2.9 2.4
Unit
V
V
V
V
mA
mA
mA
mA
AC ELECTRICAL CHARACTERISTICS (V
Symbo
f
Maximum Clock Frequency (50% Duty Cycle)
max
= 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)
CC
Parameter
(Figures 1 and 4)
t
,
PLH
t
t
t
t
t
t
TLH
t
C
Maximum Propagation Delay, Clock to Q
PHL
PLZ
PHZ
PZL
PZH
THL
C
out
in
(Figures 1 and 4)
,
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
,
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance 10 10 10 pF
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
C
Power Dissipation Capacitance (Per Flip−Flop)* 65 pF
PD
*Used to determine the no−load dynamic power consumption: PD = CPD V
2
f + ICC VCC.
CC
Guaranteed Limit
−55 to 25_C ≤ 85_C ≤ 125_C
30 24 20 MHz
31 39 47 ns
30 38 45 ns
30 38 45 ns
12 15 18 ns
15 15 15 pF
Typical @ 25°C, VCC = 5.0 V
Unit
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