ON Semiconductor MC74HCT374A User Manual

MC74HCT374A

Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs

High−Performance Silicon−Gate CMOS

The MC74HCT374A may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs.

The HCT374A is identical in pinout to the LS374.

Data meeting the setup and hold time is clocked to the outputs with the rising edge of Clock. The Output Enable does not affect the state of the flip−flops, but when Output Enable is high, the outputs are forced to the high−impedance state. Thus, data may be stored even when the outputs are not enabled.

The HCT374A is identical in function to the HCT574A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT534A, which has inverting outputs.

Features

•Output Drive Capability: 15 LSTTL Loads

•TTL/NMOS−Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 mA

•In Compliance With the JEDEC Standard No. 7.0 A Requirements

•Chip Complexity: 276 FETs or 69 Equivalent Gates

•Improvements over HCT374

♦Improved Propagation Delays

♦50% Lower Quiescent Power

♦Improved Input Noise and Latchup Immunity

•These Devices are Pb−Free and are RoHS Compliant

LOGIC DIAGRAM

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SOIC−20

TSSOP−20

DW SUFFIX

DT SUFFIX

CASE 751D

CASE 948E

PIN ASSIGNMENT

OUTPUT ENABLE

VCC

GND

CLOCK

MARKING DIAGRAMS

HCT374A

HCT

374A

AWLYYWWG

ALYWG

TSSOP−20

SOIC−20

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W

= Work Week

G or G = Pb−Free Package

(Note: Microdot may be in either location)

FUNCTION TABLE

Inputs

Output

DATA

NONINVERTING

Output

INPUTS

Enable

Clock

OUTPUTS

L,H,

No Change

CLOCK

X = don’t care

Z = high impedance

PIN 20 = VCC

ORDERING INFORMATION

OUTPUT ENABLE

PIN 10 = GND

See detailed ordering and shipping information on page 5 of

this data sheet.

♥ Semiconductor Components Industries, LLC, 2014

Publication Order Number:

September, 2014

− Rev. 12

MC74HCT374A/D

MC74HCT374A

Design Criteria	Value	Units

Internal Gate Count*	69	ea.

Internal Gate Propagation Delay	1.5	ns

Internal Gate Power Dissipation	5.0	mW

Speed Power Product	.0075	pJ

*Equivalent to a two−input NAND gate.

MAXIMUM RATINGS

Symbol	Parameter		Value	Unit

VCC	DC Supply Voltage (Referenced to GND)		–0.5 to +7.0	V
Vin	DC Input Voltage (Referenced to GND)		–0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)		–0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin		±20	mA
Iout	DC Output Current, per Pin		±35	mA
ICC	DC Supply Current, VCC and GND Pins		±75	mA
PD	Power Dissipation in Still Air,	SOIC Package†	500	mW
		TSSOP Package†	450

Tstg	Storage Temperature		–65 to +150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds		260	_C
	(SOIC or TSSOP Package)		260

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Symbol	Parameter	Min	Max	Unit

VCC	DC Supply Voltage (Referenced to GND)	4.5	5.5	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)	0	VCC	V
TA	Operating Temperature, All Package Types	–55	+125	_C
tr, tf	Input Rise and Fall Time (Figure 1)	0	500	ns

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

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MC74HCT374A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

VCC

−55 to

Symbol

Parameter

Test Conditions

25_C

≤

Unit

85 C

≤ 125 C

VIH

Minimum High−Level Input Voltage

Vout = 0.1 V or VCC – 0.1 V

4.5

2.0

|Iout| ≤ 20 mA

5.5

2.0

VIL

Maximum Low−Level Input Voltage

Vout = 0.1 V or VCC – 0.1 V

4.5

0.8

|Iout| ≤ 20 mA

5.5

0.8

VOH

Minimum High−Level Output Voltage

Vin = VIH or VIL

4.5

4.4

|Iout| ≤ 20 mA

5.5

5.4

Vin = VIH or VIL

|Iout| ≤ 6.0 mA

4.5

3.98

3.84

3.7

VOL

Maximum Low−Level Output Voltage

Vin = VIH or VIL

4.5

0.1

|Iout| ≤ 20 mA

5.5

0.1

Vin = VIH or VIL

|Iout| ≤ 6.0 mA

4.5

0.26

0.33

0.4

Iin

Maximum Input Leakage Current

Vin = VCC or GND

5.5

±0.1

±1.0

IOZ

Maximum Three−State Leakage

Output in High−Impedance State

5.5

±0.5

±5.0

±10

Current

Vin = VIL or VIH

Vout = VCC or GND

ICC

Maximum Quiescent Supply Current

Vin = VCC or GND

5.5

4.0

160

(per Package)

Iout = 0 mA

DICC

Additional Quiescent Supply Current

Vin = 2.4 V, Any One Input

≥ −55_C

25_C to 125_C

Vin = VCC or GND, Other Inputs

2.9

2.4

lout = 0 mA

5.5

1. Total Supply Current = ICC + ΣDICC.

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

−55 to 25_C

≤ 85_C

≤ 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

MHz

(Figures 1 and 4)

tPLH,

Maximum Propagation Delay, Clock to Q

tPHL

(Figures 1 and 4)

tPLZ,

Maximum Propagation Delay, Output Enable to Q

tPHZ

(Figures 2 and 5)

tPZL,

Maximum Propagation Delay, Output Enable to Q

tPZH

(Figures 2 and 5)

tTLH,

Maximum Output Transition Time, Any Output

tTHL

(Figures 1 and 4)

Cin

Maximum Input Capacitance

Cout

Maximum Three−State Output Capacitance

(Output in High−Impedance State)

Typical @ 25°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Flip−Flop)*

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

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