ON Semiconductor MC74HC4051A, MC74HC4052A, MC74HC4053A Technical data

MC74HC4051A,
MC74HC4052A,
MC74HC4053A

Analog Multiplexers /
Demultiplexers

High−Performance Silicon−Gate CMOS

The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon−gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
across the complete power supply range (from VCC to VEE).

The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal−gate MC14051AB, MC14052AB and MC14053AB. The
Channel−Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.

The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.

These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.

For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.

Features

• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (V

• Digital (Control) Power Supply Range (V

• Improved Linearity and Lower ON Resistance Than Metal−Gate

Counterparts

• Low Noise

• In Compliance With the Requirements of JEDEC Standard No. 7A

• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates

HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates

• Pb−Free Packages are Available*

− VEE) = 2.0 to 12.0 V

CC

− GND) = 2.0 to 6.0 V

CC

16

16

16

16

16

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MARKING

DIAGRAMS

16

PDIP−16

N SUFFIX

1

1

1

1

1

A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)

CASE 648

SOIC−16

D SUFFIX

CASE 751B

SOIC−16 WIDE

DW SUFFIX
CASE 751G

TSSOP−16
DT SUFFIX

CASE 948F

SOEIAJ−16

F SUFFIX
CASE 966

MC74HC405xAN

AWLYYWWG

1

16

HC405xAG

AWLYWW

1

16

AWLYWWG

1

16

1

16

74HC405xA

1

HC405xA

HC40

5xA

ALYWG

G

ALYWG

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2005

June, 2005 − Rev. 3

1 Publication Order Number:

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.

MC74HC4051A/D

MC74HC4051A, MC74HC4052A, MC74HC4053A

FUNCTION TABLE − MC74HC4051A

Single−Pole, 8−Position Plus Common Off

ANALOG

INPUTS/

OUTPUTS

CHANNEL

SELECT

INPUTS

Double−Pole, 4−Position Plus Common Off

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

ENABLE

X0

X1

X2

X3

Y0

Y1

Y2

Y3

ENABLE

LOGIC DIAGRAM

MC74HC4051A

13

X0

14

X1

15

X2

12

X3

1

X4

5

X5

2

X6

4

X7

11

A

10

B

9

C

6

PIN 16 = V
PIN 7 = V
PIN 8 = GND

LOGIC DIAGRAM

MC74HC4052A

12

14

15

11

1

5

2

4

10

A

9

B

6

MULTIPLEXER/

DEMULTIPLEXER

CC

EE

X SWITCH

Y SWITCH

3

X

13

X

3

Y

PIN 16 = V
PIN 7 = V

EE

PIN 8 = GND

COMMON
OUTPUT/
INPUT

COMMON
OUTPUTS/INPUTS

CC

Control Inputs

Select

CBA

L

L
L
L
L
L
L
L
L

H

L

L

L

L

H

L

H

H

L

H

L

H

H

H

H

X

X

ON ChannelsEnable

L
H
L
H
L
H
L
H
X

X0
X1
X2
X3
X4
X5
X6
X7

NONE

X = Don’t Care

Pinout: MC74HC4051A (Top View)

V

X2 X1 X0 X3 A B C

CC

1516 14 13 12 11 10

21 34567

X4 X6 X X7 X5 Enable VEEGND

FUNCTION TABLE − MC74HC4052A

Control Inputs

Select

BA

L

L
L
L
L

H

H
H
X

L

L

H

L
H
X

ON ChannelsEnable

Y0
Y1
Y2
Y3

NONE

X = Don’t Care

Pinout: MC74HC4052A (Top View)

V

X2 X1 X X0 X3 A B

CC

1516 14 13 12 11 10

9

8

X0
X1
X2
X3

9

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2

21 34567

8

Y0 Y2 Y Y3 Y1 Enable VEEGND

MC74HC4051A, MC74HC4052A, MC74HC4053A

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

LOGIC DIAGRAM

MC74HC4053A

Triple Single−Pole, Double−Position Plus Common Off

12

X0

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

X1

Y0

Y1

ENABLE

13

2

1

5

Z0

3

Z1

11

A

10

B

9

C

6

X SWITCH

Y SWITCH

Z SWITCH

NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch

14

X

15

Y

4

Z

PIN 16 = V
PIN 7 = V

EE

PIN 8 = GND

CC

COMMON
OUTPUTS/INPUTS

FUNCTION TABLE − MC74HC4053A

Control Inputs

Select

CBA

L

L
L
L
L
L
L
L
L

H

L

L

L

L

H

L

H

H

L

H

L

H

H

H

H

X

X

ON ChannelsEnable

L

Z0

H

Z0

L

Z0

H

Z0

L

Z1

H

Z1

L

Z1

H

Z1

X

X = Don’t Care

Pinout: MC74HC4053A (Top View)

V

YXX1X0ABC

CC

1516 14 13 12 11 10

Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1

NONE

X0
X1
X0
X1
X0
X1
X0
X1

9

21 34567

8

Y1 Y0 Z1 Z Z0 Enable VEEGND

MAXIMUM RATINGS

Symbol

V

ÎÎ

V

ÎÎ

ÎÎ

ÎÎ

Positive DC Supply Voltage (Referenced to GND)

CC

EE

V

V

I

P

T

stg

T

ОООООООООООО

Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage

IS

ОООООООООООО

Digital Input Voltage (Referenced to GND)

in

DC Current, Into or Out of Any Pin
Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

(Referenced to VEE)

EIAJ/SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

Value

– 0.5 to + 7.0

ÎÎÎ

– 0.5 to + 14.0

– 7.0 to + 5.0

VEE − 0.5 to

VCC + 0.5

ÎÎÎ

– 0.5 to VCC + 0.5

± 25

750
500

ÎÎÎ

450

– 65 to + 150

260

ÎÎÎ

Unit

Î

Î

mA

mW

Î

Î

_C
_C

This device contains protection

V

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must

V
V

be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir­cuit. For proper operation, Vin and
V

V

should be constrained to the

out

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

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3

MC74HC4051A, MC74HC4052A, MC74HC4053A

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

l

RECOMMENDED OPERATING CONDITIONS

Symbol

V

ÎÎ

V

Positive DC Supply Voltage (Referenced to GND)

CC

ОООООООООООО

Negative DC Supply Voltage, Output (Referenced to

EE

GND)

V

Analog Input Voltage

IS

V

Digital Input Voltage (Referenced to GND)

in

VIO*

ÎÎ

ÎÎ

T

tr, t

Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types

A

Input Rise/Fall Time VCC = 2.0 V

f

(Channel Select or Enable Inputs) VCC = 3.0 V

ОООООООООООО

ОООООООООООО

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be

drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

Parameter

(Referenced to VEE)

VCC = 4.5 V
VCC = 6.0 V

Min

2.0

2.0

Î

− 6.0

V

EE

GND

– 55

0
0

Î

0

Î

0

Max

6.0

12.0

Î

GND

V

CC

V

CC

1.2

+ 125

1000

600

Î

500

Î

400

Unit

V

Î

V

V
V
V

_C

ns

Î

Î

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V

Symbo

V

IH

V

IL

I

in

I

CC

Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs

Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs

Maximum Input Leakage Current,
Channel−Select or Enable Inputs

Maximum Quiescent Supply
Current (per Package)

Parameter Condition

Ron = Per Spec 2.0

Ron = Per Spec 2.0

Vin = VCC or GND,
VEE = − 6.0 V

Channel Select, Enable and
VIS = VCC or GND; VEE = GND
VIO = 0 V VEE = − 6.0

= GND, Except Where Noted

EE

V

CC

V

3.0

4.5

6.0

3.0

4.5

6.0

Guaranteed Limit

−55 to 25°C ≤85°C ≤125°C

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

6.0 ± 0.1 ± 1.0 ± 1.0

6.0

6.0

1

4

10
40

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

20
80

Unit

V

V

mA

mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor H igh−Speed C MOS D ata B ook ( DL129/D).

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4

MC74HC4051A, MC74HC4052A, MC74HC4053A

l

l

DC CHARACTERISTICS — Analog Section

Guaranteed Limit

Symbo

R

on

DR

on

I

off

Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to

Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package

Maximum Off−Channel Leakage
Current, Any One Channel

Parameter Condition V

VEE; IS ≤ 2.0 mA
(Figures 1, 2)

Vin = VIL or VIH; VIS = VCC or

(Endpoints); IS ≤ 2.0 mA

V

EE

(Figures 1, 2)
Vin = VIL or VIH;

VIS = 1/2 (VCC − VEE);
IS ≤ 2.0 mA

Vin = VIL or VIH;
VIO = VCC − VEE;

CC

4.5

4.5

6.0

4.5

4.5

6.0

4.5

4.5

6.0

6.0 − 6.0 0.1 0.5 1.0

Switch Off (Figure 3)

Maximum Off−ChannelHC4051A
Leakage Current, HC4052A
Common Channel HC4053A

I

Maximum On−ChannelHC4051A

on

Leakage Current, HC4052A
Channel−to−Channel HC4053A

AC CHARACTERISTICS (C

Symbo

t

,

Maximum Propagation Delay, Channel−Select to Analog Output

PLH

t

(Figure 9)

PHL

t

,

Maximum Propagation Delay, Analog Input to Analog Output

PLH

t

(Figure 10)

PHL

t

,

Maximum Propagation Delay, Enable to Analog Output

PLZ

t

(Figure 11)

PHZ

t

,

Maximum Propagation Delay, Enable to Analog Output

PZL

t

(Figure 11)

PZH

C

Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF

in

C

Maximum Capacitance Analog I/O 35 35 35 pF

I/O

= 50 pF, Input tr = tf = 6 ns)

L

Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 4)

Vin = VIL or VIH;
Switch−to−Switch =
VCC − VEE; (Figure 5)

Parameter

6.0

6.0

6.0

6.0

6.0

6.0

(All Switches Off) Common O/I: HC4051A

HC4052A
HC4053A

Feedthrough 1.0 1.0 1.0

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D)

C

Power Dissipation Capacitance (Figure 13)* HC4051A

PD

HC4052A
HC4053A

*Used to determine t he no−load dynamic p ower consumption: PD = CPD V

2

f + ICC VCC. For load considerations, see C hapter 2 o f t h e

CC

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

−55 to 25°C ≤85°C ≤125°C

V

EE

0.0

− 4.5

− 6.0

0.0

− 4.5

− 6.0

0.0

− 4.5

− 6.0

− 6.0

− 6.0

− 6.0

− 6.0

− 6.0

− 6.0

V

CC

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

190
120
100

150
100

80
30

12
10

0.2

0.1

0.1

0.2

0.1

0.1

240
150
125

190
125
100

35
15
12

2.0

1.0

1.0

2.0

1.0

1.0

280
170
140

230
140
115

40
18
14

4.0

2.0

2.0

4.0

2.0

2.0

Guaranteed Limit

−55 to 25°C ≤85°C ≤125°C

270

90
59
45

40
25
12
10

160

70
48
39

245
115

49
39

130

80
50

320
110

79
65

60
30
15
13

200

95
63
55

315
145

69
58

130

80
50

350
125

85
75

70
32
18
15

220
110

76
63

345
155

83
67

130

80
50

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

45
80
45

Unit

W

W

mA

mA

Unit

ns

ns

ns

ns

pF

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5

MC74HC4051A, MC74HC4052A, MC74HC4053A

l

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Symbo

BW Maximum On−Channel Bandwidth

or Minimum Frequency Response
(Figure 6)

− Off−Channel Feedthrough Isolation
(Figure 7)

− Feedthrough Noise.
Channel−Select Input to Common
I/O (Figure 8)

− Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051A)

THD Total Harmonic Distortion

(Figure 14)

*Limits not tested. Determined by design and verified by qualification.

Parameter Condition

fin = 1MHz Sine Wave; Adjust fin Voltage
to Obtain 0dBm at VOS; Increase f
Frequency Until dB Meter Reads −3dB;
RL = 50W, CL = 10pF

fin = Sine Wave; Adjust fin Voltage to
Obtain 0dBm at V

IS

fin = 10kHz, RL = 600W, CL = 50pF

fin = 1.0MHz, RL = 50W, CL = 10pF

Vin ≤ 1MHz Square Wave (tr = tf = 6ns);
Adjust RL at Setup so that IS = 0A;
Enable = GND RL = 600W, CL = 50pF

RL = 10kW, CL = 10pF

fin = Sine Wave; Adjust fin Voltage to
Obtain 0dBm at V

IS

fin = 10kHz, RL = 600W, CL = 50pF

fin = 1.0MHz, RL = 50W, CL = 10pF

fin = 1kHz, RL = 10kW, CL = 50pF
THD = THD

measured

VIS = 4.0VPP sine wave
VIS = 8.0VPP sine wave

VIS = 11.0VPP sine wave

− THD

source

V

in

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

V

CC

V

EE

V

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

Limit*

25°C

‘51 ‘52 ‘53

80

95
95
95

120
120
120

80
80

−50

−50

−50

−40

−40

−40
25

105
135

35

145
190

−50

−50

−50

−60

−60

−60

Unit

MHz

dB

mV

dB

PP

%

2.25

4.50

6.00

−2.25

−4.50

−6.00

0.10

0.08

0.05

300

250

180

160

140

200

150

100

, ON RESISTANCE (OHMS)

on

R

50

125°C

25°C

−55 °C

120

100

80

60

, ON RESISTANCE (OHMS)

on

40

R

20

0

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

EE

0

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25

2.0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

2.5 2.75 3.0

EE

Figure 1a. Typical On Resistance, VCC − VEE = 2.0 V Figure 1b. Typical On Resistance, VCC − VEE = 3.0 V

125°C

25°C

−55 °C

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6

MC74HC4051A, MC74HC4052A, MC74HC4053A

120

100

80

60

40

, ON RESISTANCE (OHMS)

on

R

20

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

125°C

25°C

−55 °C

EE

105

90

75

60

45

, ON RESISTANCE (OHMS)

30

on

R

15

0

0 1.0 2.0 3.0 4.0 5.0 6.03.5 4.5 5.5

0.5 1.5 2.5

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

125°C

−55 °C

EE

Figure 1c. Typical On Resistance, VCC − VEE = 4.5 V Figure 1d. Typical On Resistance, VCC − VEE = 6.0 V

80

70

60

50

40

30

, ON RESISTANCE (OHMS)

20

on

R

10

0

−4.5 −3.5

−2.5 −1.5 −0.5 0.5 1.5 2.5 3.5 4.5

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

Figure 1e. Typical On Resistance, VCC − VEE = 9.0 V

125°C

25°C

−55 °C

EE

60

50

40

30

20

, ON RESISTANCE (OHMS)

on

R

10

0

−6.0 −5.0

−4.0 −3.0 −2.0 2.0 3.0 4.0 5.0 6.0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

−1.0

1.00

125°C

−55 °C

EE

Figure 1f. Typical On Resistance, VCC − VEE = 12.0 V

25°C

25°C

PROGRAMMABLE

POWER

SUPPLY

+−

ANALOG IN COMMON OUT

PLOTTER

MINI COMPUTER

DEVICE

UNDER TEST

GND

V

EE

DC ANALYZER

V

CC

Figure 2. On Resistance Test Set−Up

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MC74HC4051A, MC74HC4052A, MC74HC4053A

V

CC

V

CC

V

EE

16

OFF

V

CC

A

NC

V

IH

OFF

6

COMMON O/I

7
8

V

EE

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set−Up

V

CC

A

ON

V

EE

V

CC

ANALOG I/O

OFF

16

COMMON O/I

V

CC

N/C

V

CC

V

V

EE

V

CC

ANALOG I/O

V

IH

6

16

OFF

OFF

CC

COMMON O/I

7
8

V

EE

Figure 4. Maximum Off Channel Leakage Current,

Common Channel, Test Set−Up

V

CC

V

OS

ON

16

dB

METER

R

CL*

L

0.1mF

f

in

V

IL

6
7
8

V

EE

Figure 5. Maximum On Channel Leakage Current,

Channel to Channel, Test Set−Up

V

CC

V

IS

0.1mF

f

in

R

OFF

L

V

16

OS

dB

METER

R

CL*

L

6
7
8

V

VIL or V

EE

IH

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 7. Off Channel Feedthrough Isolation,

Test Set−Up

6
7
8

V

EE

*Includes all probe and jig capacitance

Figure 6. Maximum On Channel Bandwidth,

Test Set−Up

V

CC

R

L

16

ON/OFF

ANALOG I/O

OFF/ON

R

L

6
7

11

V

GND

CC

Vin ≤ 1 MHz

tr = tf = 6 ns

8

V

EE

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 8. Feedthrough Noise, Channel Select to

Common Out, Test Set−Up

COMMON O/I

R

L

V

CC

TEST
POINT

CL*

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8

CHANNEL

SELECT

ANALOG

OUT

t

PLH

50%

MC74HC4051A, MC74HC4052A, MC74HC4053A

V

V

CC

ANALOG I/O

GND

t

PHL

50%

V

CC

ON/OFF

OFF/ON

CC

16

COMMON O/I

CL*

6
7
8

CHANNEL SELECT

*Includes all probe and jig capacitance

TEST
POINT

Figure 9a. Propagation Delays, Channel Select

to Analog Out

ANALOG

ANALOG

OUT

IN

t

PLH

50%

50%

Figure 10a. Propagation Delays, Analog In

to Analog Out

t

ENABLE

ANALOG

OUT

ANALOG

OUT

f

50%

50%

t

t

PZL

PZH

t

t

t

r

PLZ

PHZ

Figure 11a. Propagation Delays, Enable to

Analog Out

90%
50%
10%

10%

90%

t

PHL

V

CC

GND

HIGH
IMPEDANCE

V

OL

V

OH

HIGH
IMPEDANCE

V

CC

GND

Figure 9b. Propagation Delay, Test Set−Up Channel

Select to Analog Out

V

CC

16

ANALOG I/O

ON

COMMON O/I

TEST
POINT

CL*

6
7
8

*Includes all probe and jig capacitance

Figure 10b. Propagation Delay, Test Set−Up

Analog In to Analog Out

POSITION 1 WHEN TESTING t

1

2

V

CC

1

2

POSITION 2 WHEN TESTING t

ANALOG I/O

ON/OFF

ENABLE

6

V

16

7
8

AND t

PHZ
PLZ

CC

AND t

PZH

PZL

1kW

CL*

Figure 11b. Propagation Delay, Test Set−Up

Enable to Analog Out

TEST
POINT

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9

MC74HC4051A, MC74HC4052A, MC74HC4053A

V

V

IS

V

CC

ANALOG I/O

V

EE

ON/OFF

OFF/ON

6
7
8

CHANNEL SELECT

Test Set−Up

R

f

in

0.1mF

L

V

EE

R

L

6
7
8

*Includes all probe and jig capacitance

Figure 12. Crosstalk Between Any Two

ON

OFF

16

R

L

CL*

V

OS

R

L

CL*

Figure 13. Power Dissipation Capacitance,

Switches, Test Set−Up

CC

A

16

COMMON O/I

11

NC

V

CC

dB

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

FUNDAMENTAL FREQUENCY

DEVICE

SOURCE

1.0 2.0 3.125

FREQUENCY (kHz)

V

IS

0.1mF

f

in

6
7
8

V

EE

V

CC

16

ON

*Includes all probe and jig capacitance

V

OS

TO

DISTORTION

CL*

METER

R

L

Figure 14a. Total Harmonic Distortion, Test Set−Up Figure 14b. Plot, Harmonic Distortion

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example:

VCC = +5V = logic high

GND = 0V = logic low

The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage shoul d n o t exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is ten volts. Therefore,
using the configuration of Figure 15, a maximum analog
signal of ten volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and

outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.

Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:

VCC − GND = 2 to 6 volts

VEE − GND = 0 to −6 volts

VCC − VEE = 2 to 12 volts

and VEE ≤ GND

When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in Figure

16. These diodes should be able to absorb the maximum
anticipated current surges during clipping.

http://onsemi.com

10

MC74HC4051A, MC74HC4052A, MC74HC4053A

+5V

−5V

+5V

V

V

V

CC

CC

D

16

x

D

x

V

EE

ANALOG

SIGNAL

−5V

V

+5V

16

ANALOG

ON

6
7
8

SIGNAL

11
10

TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS

9

+5V

−5V

CC

D

x

ON/OFF

D

x

V

EE

7
8

V

EE

Figure 15. Application Example Figure 16. External Germanium or

Schottky Clipping Diodes

+5V

16

ANALOG

EE

SIGNAL

ON/OFF

ANALOG

SIGNAL

+5V

+5V

V

+5V

EE

V

EE

ANALOG

SIGNAL

ON/OFF

R*R R

6

11

7

10

8

V

EE

9

* 2K ≤ R ≤ 10K

LSTTL/NMOS

CIRCUITRY

V

EE

6
7
8

16

11
10

9

+5V

ANALOG

SIGNAL

HCT

BUFFER

+5V

V

EE

+5V

LSTTL/NMOS

CIRCUITRY

a. Using Pull−Up Resistors b. Using HCT Interface

ENABLE

Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs

11

A

10

B

9

C

6

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

13

X0

14

X1

15

X2

12

X3

1

X4

5

X5

2

X6

4

X7

Figure 18. Function Diagram, HC4051A

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11

3

X

MC74HC4051A, MC74HC4052A, MC74HC4053A

ENABLE

10

A

9

B

6

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

12

X0

14

X1

15

X2

11

X3

13

X

1

Y0

5

Y1

2

Y2

4

Y3

3

Y

ENABLE

Figure 19. Function Diagram, HC4052A

11

A

10

B

9

C

6

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

13

X1

12

X0

14

X

1

Y1

2

Y0

15

Y

3

Z1

5

Z0

4

Z

Figure 20. Function Diagram, HC4053A

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12

MC74HC4051A, MC74HC4052A, MC74HC4053A

ORDERING INFORMATION

Device Package Shipping

MC74HC4051AN PDIP−16 500 Units / Box
MC74HC4051ANG PDIP−16

(Pb−Free)
MC74HC4051AD SOIC−16 48 Units / Rail
MC74HC4051ADG SOIC−16

(Pb−Free)
MC74HC4051ADR2 SOIC−16 2500 Units / Tape & Reel
MC74HC4051ADR2G SOIC−16

(Pb−Free)
MC74HC4051ADT TSSOP−16* 96 Units / Rail
MC74HC4051ADTG TSSOP−16* 96 Units / Rail
MC74HC4051ADTR2 TSSOP−16* 2500 Units / Tape & Reel
MC74HC4051ADTR2G TSSOP−16* 2500 Units / Tape & Reel
MC74HC4051ADW SOIC−16 WIDE 48 Units / Rail
MC74HC4051ADWG SOIC−16 WIDE

(Pb−Free)
MC74HC4051ADWR2 SOIC−16 WIDE 1000 Units / Tape & Reel
MC74HC4051ADWR2G SOIC−16 WIDE

(Pb−Free)
MC74HC4051AFEL SOEIAJ−16 2000 Units / Tape & Reel
MC74HC4051AFELG SOEIAJ−16

(Pb−Free)
MC74HC4052AN PDIP−16 500 Units / Box
MC74HC4052ANG PDIP−16

(Pb−Free)
MC74HC4052AD SOIC−16 48 Units / Rail
MC74HC4052ADG SOIC−16

(Pb−Free)
MC74HC4052ADR2 SOIC−16 2500 Units / Tape & Reel
MC74HC4052ADR2G SOIC−16

(Pb−Free)
MC74HC4052ADT TSSOP−16* 96 Units / Rail
MC74HC4052ADTG TSSOP−16* 96 Units / Rail
MC74HC4052ADTR2 TSSOP−16* 2500 Units / Tape & Reel
MC74HC4052ADTR2G TSSOP−16* 2500 Units / Tape & Reel
MC74HC4052ADW SOIC−16 WIDE 48 Units / Rail
MC74HC4052ADWG SOIC−16 WIDE

(Pb−Free)
MC74HC4052ADWR2 SOIC−16 WIDE 1000 Units / Tape & Reel
MC74HC4052AF SOEIAJ−16 50 Units / Rail
MC74HC4052AFG SOEIAJ−16

(Pb−Free)
MC74HC4052AFEL SOEIAJ−16 2000 Units / Tape & Reel
MC74HC4052AFELG SOEIAJ−16

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

500 Units / Box

48 Units / Rail

2500 Units / Tape & Reel

48 Units / Rail

1000 Units / Tape & Reel

2000 Units / Tape & Reel

500 Units / Box

48 Units / Rail

2500 Units / Tape & Reel

48 Units / Rail

50 Units / Rail

2000 Units / Tape & Reel

†

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13

MC74HC4051A, MC74HC4052A, MC74HC4053A

ORDERING INFORMATION

Device Package Shipping

MC74HC4053AN PDIP−16 500 Units / Box
MC74HC4053ANG PDIP−16

(Pb−Free)
MC74HC4053AD SOIC−16 48 Units / Rail
MC74HC4053ADG SOIC−16

(Pb−Free)
MC74HC4053ADR2 SOIC−16 2500 Units / Tape & Reel
MC74HC4053ADR2G SOIC−16

(Pb−Free)
MC74HC4053ADT TSSOP−16* 96 Units / Rail
MC74HC4053ADTG TSSOP−16* 96 Units / Rail
MC74HC4053ADTR2 TSSOP−16* 2500 Units / Tape & Reel
MC74HC4053ADTR2 TSSOP−16* 2500 Units / Tape & Reel
MC74HC4053ADW SOIC−16 WIDE 48 Units / Rail
MC74HC4053ADWG SOIC−16 WIDE

(Pb−Free)
MC74HC4053ADWR2 SOIC−16 WIDE 1000 Units / Tape & Reel
MC74HC4053ADWR2G SOIC−16 WIDE

(Pb−Free)
MC74HC4053AF SOEIAJ−16 50 Units / Rail
MC74HC4053AFG SOEIAJ−16

(Pb−Free)
MC74HC4053AFEL SOEIAJ−16 2000 Units / Tape & Reel
MC74HC4053AFELG SOEIAJ−16

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

500 Units / Box

48 Units / Rail

2500 Units / Tape & Reel

48 Units / Rail

1000 Units / Tape & Reel

50 Units / Rail

2000 Units / Tape & Reel

†

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14

MC74HC4051A, MC74HC4052A, MC74HC4053A

PDIP−16

PACKAGE DIMENSIONS

N SUFFIX

CASE 648−08

ISSUE T

−A−

916

B

18

F

H

G

D

16 PL

0.25 (0.010) T

C

S

−T−

K

M

A

SEATING
PLANE

J

M

CASE 751B−05

L

SOIC−16

D SUFFIX

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77

M

G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30

L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES

____

−T−

−A−

16 9

−B−

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

M

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15

R X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

S

_

F

J

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

____

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

MC74HC4051A, MC74HC4052A, MC74HC4053A

SOIC−16 WIDE

DW SUFFIX

CASE 751G−03

ISSUE C

16 9

M

B

H8X

M

0.25

0.25 B

14X

D

A

E

q

_

h X 45

81

B16X

M

S

A

T

B

S

A

SEATING

T

PLANE

C

e

A1

L

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 10.15 10.45

E 7.40 7.60
e 1.27 BSC

H 10.05 10.55

h 0.25 0.75
L 0.50 0.90
q 0 7

__

TSSOP−16
DT SUFFIX

CASE 948F−01

ISSUE A

0.10 (0.004)

−T−

SEATING
PLANE

L

U0.15 (0.006) T

PIN 1
IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

16X REFK

0.10 (0.004) V

M

S

U

T

S

K

K1

16

9

J1

B

−U−

1

8

J

N

A

SECTION N−N

0.25 (0.010)

M

−V−
N

F

DETAIL E

C

DETAIL E

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

−W−

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

INCHESMILLIMETERS

G

http://onsemi.com

16

SOEIAJ−16

16 9

1

Z

D

e

b

0.13 (0.005)

M

MC74HC4051A, MC74HC4052A, MC74HC4053A

PACKAGE DIMENSIONS

F SUFFIX

CASE 966−01

ISSUE O

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A
A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

L

1.10 1.50 0.043 0.059

E

0

M

Q

0.70 0.90 0.028 0.035

1

−−− 0.78 −−− 0.031

Z

8

H

E

E

A

A

1

0.10 (0.004)

VIEW P

L

E

Q

1

M

_

L

DETAIL P

c

INCHES

10

_

_

10

0

_

_

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17

MC74HC4051A, MC74HC4052A, MC74HC4053A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [e-mail]

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Japan: ON Semiconductor, Japan Customer Focus Center

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Phone: 81−3−5773−3850

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ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your
local Sales Representative.

MC74HC4051A/D

18