ON Semiconductor MC74HC32A Technical data

MC74HC32A

Quad 2−Input OR Gate

High−Performance Silicon−Gate CMOS

The MC74HC32A is identical in pinout to the LS32. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

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Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1A

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 48 FETs or 12 Equivalent Gates

• Pb−Free Packages are Available*

MARKING

DIAGRAMS

14

PDIP−14

4

1

14

1

14

1

N SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14
DT SUFFIX

CASE 948G

MC74HC32AN

AWLYYWWG

1

14

1

14

1

14

HC32AG

AWLYWW

HC

32A

ALYW



*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

May, 2005 − Rev. 8

1 Publication Order Number:

14

SOEIAJ−14

F SUFFIX

1

A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
 = Pb−Free Package
(Note: Microdot may be in either location)

CASE 965

74HC32A

ALYWG

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

MC74HC32A/D

MC74HC32A

Pinout: 14−Lead Packages (Top View)

B4 A4 Y4 B3 A3 Y3

V

CC

1314 12 11 10 9 8

21 34567

A1 B1 Y1 A2 B2 Y2 GND

FUNCTION TABLE

Inputs Output

AB

L
L
H
H

L

H

L

H

Y

L
H
H
H

A1

B1

A2

B2

A3

B3

A4

B4

LOGIC DIAGRAM

1

2

4

5

9

10

12

13

PIN 14 = V
PIN 7 = GND

3

Y1

6

Y2

Y = A+B

8

Y3

11

Y4

CC

ORDERING INFORMATION

Device Package Shipping

MC74HC32AN PDIP−14 500 Units / Rail
MC74HC32ANG PDIP−14

(Pb−Free)
MC74HC32AD SOIC−14 55 Units / Rail
MC74HC32ADG SOIC−14

(Pb−Free)
MC74HC32ADR2 SOIC−14 2500 Units / Reel
MC74HC32ADR2G SOIC−14

(Pb−Free)
MC74HC32ADTR2 TSSOP−14* 2500 Units / Reel
MC74HC32ADTR2G TSSOP−14* 2500 Units / Reel
MC74HC32AFEL SOEIAJ−14 2000 Units / Reel
MC74HC32AFELG SOEIAJ−14

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

500 Units / Rail

55 Units / Rail

2500 Units / Reel

2000 Units / Reel

†

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2

MC74HC32A

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

MAXIMUM RATINGS

Symbol

V

V

ÎÎ

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

T

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/C from 65 to 125C

SOIC Package: – 7 mW/C from 65 to 125C
TSSOP Package: − 6.1 mW/C from 65 to 125C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

Value

– 0.5 to + 7.0

– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5

± 20
± 25
± 50

750
500

ÎÎÎ

450

– 65 to + 150

ÎÎÎ

260

Unit

mW

Î

Î

V
V

V
mA
mA
mA

C
C

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir­cuit. For proper operation, V
V

should be constrained to the

out

range GND  (V

in

or V

)  VCC.

out

in

and

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V

CC

Unused outputs must be left open.

).

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

ÎÎ

T

A

tr, t

f

ÎÎ

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to

out

ОООООООООООО

GND)
Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V

(Figure 1) V

ОООООООООООО

Parameter

V

= 4.5 V

CC

= 6.0 V

CC

Min

2.0
0

Î

– 55

0
0

Î

0

Max

6.0

V

CC

Î

+ 125

1000

500

Î

400

Unit

Î

Î

V
V

C

ns

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