ON Semiconductor MC74HC273A Technical data

MC74HC273A

2

Octal D Flip−Flop with Common Clock and Reset

High−Performance Silicon−Gate CMOS

The MC74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of eight D flip−flops with common Clock and Reset inputs. Each flip−flop is loaded with a low−to−high transition of

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MARKING

DIAGRAMS

the Clock input. Reset is asynchronous and active low.

Features

0

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

1

20

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

1

PDIP−20 N SUFFIX CASE 738

SOIC−20

DW SUFFIX CASE 751D

• Chip Complexity: 264 FETs or 66 Equivalent Gates

20

MC74HC273AN

AWLYYWWG

1

20

74HC273A

AWLYYWWG

1

• Pb−Free Packages are Available*

20

TSSOP−20 DT SUFFIX

1

CASE 948E

1

HC

273A

ALYWG

G

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

July, 2005 − Rev. 10

1 Publication Order Number:

20

1

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

SOEIAJ−20

F SUFFIX

CASE 967

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location)

ORDERING INFORMATION

74HC273A

AWLYWWG

1

MC74HC273A/D

MC74HC273A

PIN ASSIGNMENT

Î

LOGIC DIAGRAM

3

D0

4

D1

7

D2

DATA

INPUTS

Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product

ООООООООО

*Equivalent to a two−input NAND gate.

8

D3

13

D4

14

D5

17

D6

18

D7

11

CLOCK

1

RESET

Design Criteria

2

Q0

5

Q1

6

Q2

9

Q3

12

Q4

15

Q5

16

Q6

19

Q7

PIN 20 = V PIN 10 = GND

Value

66

1.5

5.0

.0075

ÎÎ

NONINVERTING

OUTPUTS

CC

Units

ea ns

mW

pJ

Î

RESET

Q0

D0

D1

Q1 5

Q2

D2

D3

Q3

GND

1

2

3

4

6

7

8

9

10

20

V

CC

19

Q7

18

D7

17

D6

16

Q6

15

Q5

14

D5

13

D4

12

Q4

11

CLOCK

FUNCTION TABLE

Inputs Output

Reset Clock D Q

LXX L HHH HLL H L X No Change H X No Change

ORDERING INFORMATION

Device Package Shipping

MC74HC273AN PDIP−20 18 Units / Rail MC74HC273ANG SOIC−20

18 Units / Rail

(Pb−Free) MC74HC273ADW SOIC−20 WIDE 38 Units / Rail MC74HC273ADWG SOIC−20 WIDE

38 Units / Rail

(Pb−Free) MC74HC273ADWR2 SOIC−20 WIDE 1000 Tape & Reel MC74HC273ADWR2G SOIC−20 WIDE

1000 Tape & Reel

(Pb−Free) MC74HC273ADT TSSOP−20* 75 Units / Rail MC74HC273ADTG TSSOP−20* 75 Units / Rail MC74HC273ADTR2 TSSOP−20* 2500 Tape & Reel MC74HC273ADTR2G TSSOP−20* 2500 Tape & Reel MC74HC273AF SOEIAJ−20 40 Units / Rail MC74HC273AFG SOEIAJ−20

40 Units / Rail

(Pb−Free) MC74HC273AFEL SOEIAJ−20 2000 Tape & Reel MC74HC273AFELG SOEIAJ−20

2000 Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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2

MC74HC273A

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

MAXIMUM RATINGS

Symbol

V

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

T

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 25 ± 50

750 500

ÎÎÎ

450

– 65 to + 150

260

ÎÎÎ

Unit

mA mA mA

mW

Î

_C _C

This device contains protection

V V V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

) v VCC.

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

T

A

tr, t

f

ÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

ОООООООООООО

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

VCC = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎ

Symbol

V

ÎÎ

V

ÎÎ

V

OH

ÎÎ

V

OL

ÎÎ

ОООООООО

Minimum High−Level Input Voltage

IH

ОООООООО

Maximum Low−Level Input Voltage

IL

ОООООООО

Parameter

Minimum High−Level Output

ОООООООО

Voltage

ОООООООО

Maximum Low−Level Output Voltage

ОООООООО

ООООООО

Test Conditions

V

= VCC – 0.1 V

out

|I

| v 20 mA

out

ООООООО

V

= 0.1 V

out

|I

| v 20 mA

out

ООООООО

Vin = V

IH

ООООООО

|I

| v 20 mA

out

Vin = V

IH

ООООООО

Vin = V

IL

|I

| v 20 mA

out

ООООООО

Vin = V

IL

ООООООО

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Min

2.0 0

– 55

0 0 0

|I |I |I

3

out out out

Max

6.0

V

CC

+ 125

1000

ÎÎ

500 400

ÎÎ

| v 2.4 mA | v 6.0 mA | v 7.8 mA

Unit

V V

_C

ns

Î

V

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

4.5

Î

6.0

2.0

Î

4.5

6.0

3.0

Î

4.5

6.0

Î

2.0

4.5

6.0

Î

3.0

4.5

Î

6.0

CC

V

Guaranteed Limit

– 55 to

ÎÎ

25_C

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

0.9

1.35

ÎÎ

1.8

1.9

ÎÎ

4.4

5.9

2.48

ÎÎ

3.98

5.48

ÎÎ

0.1

ÎÎ

0.26

ÎÎ

0.26

ÎÎ

v 85_C

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

0.9

1.35

ÎÎ

1.8

1.9

ÎÎ

4.4

5.9

2.34

ÎÎ

3.84

5.34

ÎÎ

0.1

ÎÎ

0.33

ÎÎ

0.33

ÎÎ

v 125_C

1.5

2.1

ÎÎ

3.15

4.2

ÎÎ

0.5

0.9

1.35

ÎÎ

1.8

1.9

ÎÎ

4.4

5.9

2.2

ÎÎ

3.7

5.2

ÎÎ

0.1

ÎÎ

0.4

ÎÎ

0.4

Unit

V

MC74HC273A

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

l

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

6.0

CC

– 55 to

25_C

± 0.1 ± 0.5

ÎÎ

4.0

ÎÎ

v 85_C

± 1.0 ± 5.0

ÎÎ

40

ÎÎ

v 125_C

± 1.0

± 10

ÎÎ

160

ÎÎ

Unit

mA mA

mA

V

Symbol

I

in

I

OZ

ÎÎ

I

CC

ÎÎ

Parameter

Maximum Input Leakage Current Maximum Three−State Leakage

Current

ОООООООО

Maximum Quiescent Supply Current (per Package)

ОООООООО

Vin = VCC or GND Output in High−Impedance State

Vin = VIL or V V

Vin = VCC or GND I

Test Conditions

ООООООО

= VCC or GND

out

= 0 mA

ООООООО

out

IH

Î

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

L

Guaranteed Limit

ÎÎ

Symbo

f

max

ÎÎ

t

PLH

ÎÎ

t

PHL

ÎÎ

t

PHL

ÎÎ

t

TLH

ÎÎ

t

THL

ÎÎ

C

in

ОООООООООООООООО

Parameter

Maximum Clock Frequency (50% Duty Cycle)

ОООООООООООООООО

(Figures 1 and 4)

ОООООООООООООООО

Maximum Propagation Delay, Clock to Q

ОООООООООООООООО

(Figures 1 and 4)

ОООООООООООООООО

Maximum Propagation Delay, Reset to Q

ОООООООООООООООО

(Figures 2 and 4)

ОООООООООООООООО

Maximum Output Transition Time, Any Output

ОООООООООООООООО

(Figures 1 and 4)

ОООООООООООООООО

Maximum Input Capacitance

V

Î

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

CC

– 55 to

25_C

6.0

ÎÎ

15 30

ÎÎ

35

145

ÎÎ

90 29

ÎÎ

25

145

ÎÎ

90 29

ÎÎ

25 75

ÎÎ

27 15

ÎÎ

13 10

v 85_C

5.0

ÎÎ

10 24

ÎÎ

28

180

ÎÎ

120

36

ÎÎ

31

180

ÎÎ

120

36

ÎÎ

31 95

ÎÎ

32 19

ÎÎ

16 10

v 125_C

4.0

ÎÎ

8.0 20

ÎÎ

24

220

ÎÎ

140

44

ÎÎ

38

220

ÎÎ

140

44

ÎÎ

38

110

ÎÎ

36 22

ÎÎ

19 10

Unit

MHz

ns

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

Power Dissipation Capacitance (Per Enabled Output)*

PD

*Used to determine t he no−load d ynamic p ower consumption: PD = CPD V

2

f + ICC VCC. For load considerations, see Chapter 2 of t h e

CC

48

pF

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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4

MC74HC273A

Î

l

Î

TIMING REQUIREMENTS (C

ÎÎ

Symbo

t

su

ÎÎ

t

ÎÎ

t

rec

ÎÎ

t

ÎÎ

t

ÎÎ

tr, t

ÎÎ

ООООООООООО

Parameter

Minimum Setup Time, Data to Clock

ООООООООООО

Minimum Hold Time, Clock to Data

h

ООООООООООО

Minimum Recovery Time, Reset Inactive to Clock

ООООООООООО

Minimum Pulse Width, Clock

w

ООООООООООО

Minimum Pulse Width, Reset

w

ООООООООООО

Maximum Input Rise and Fall Times

f

ООООООООООО

= 50 pF, Input tr = tf = 6.0 ns)

L

Î

Figure

3

Î

3

Î

2

Î

1

Î

2

Î

1

Î

V

CC

Volts

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

4.5

Î

6.0

– 55 to 25_C

Min

Max

60 23

Î

12 10

Î

3.0

Î

3.0

Î

5.0

Î

5.0

Î

60 23

Î

12 10

Î

60 23

Î

12 10

Î

1000

800 500

ÎÎÎ

400

Guaranteed Limit

v 85_C

Min

Max

75 27

Î

15 13

Î

3.0

Î

3.0

Î

5.0

Î

5.0

Î

75 27

Î

15 13

Î

75 27

Î

15 13

Î

1000

800 500

ÎÎÎ

400

v 125_C

Min

Max

90 32

Î

18 15

Î

3.0

Î

3.0

Î

5.0

Î

5.0

Î

90 32

Î

18 15

Î

90 32

Î

18 15

Î

1000

800 500

ÎÎÎ

400

Unit

ns

Î

ns

Î

ns

Î

ns

Î

ns

Î

ns

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5

CLOCK

MC74HC273A

SWITCHING WAVEFORMS

t

50%

w

50%

t

PHL

V

CC

GND

t

rec

50%

V

CC

GND

t

f

V

CC

RESET

GND

1/f

max

t

PHL

Q

50%

10%

90%

t

r

t

w

t

PLH

90%

Q

50%

10%

t

TLH

t

THL

CLOCK

DATA

CLOCK

50%

DEVICE UNDER

TEST

Figure 1.

VALID

t

su

Figure 3.

OUTPUT

t

h

50%

TEST POINT

CL*

V

CC

GND

V

CC

GND

DATA

INPUTS

D0

D1

D2

D3

D4

D5

Figure 2.

C

3

4

7

8

13

14

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

C

Q

D

R

2

Q0

5

Q1

6

Q2

9

Q3

NONINVERTING

OUTPUTS

12

Q4

15

Q5

*Includes all probe and jig capacitance

Figure 4. Test Circuit

D6

D7

Figure 5. Expanded Logic Diagram

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6

C

17

18

Q

D

R

C

Q

D

R

16

Q6

19

Q7

11

1

MC74HC273A

SOIC−20

PACKAGE DIMENSIONS

PDIP−20

N SUFFIX

PLASTIC DIP PACKAGE

CASE 738−03

ISSUE E

−T−

SEATING PLANE

−A−

20

11

B

1

10

C

L

K

M

E

FG

N

D 20 PL

0.25 (0.010) T

J 20 PL

M

A

0.25 (0.010) T

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022 E F G 2.54 BSC0.100 BSC

J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC M 0 15 0 15 N 0.51 1.010.020 0.040

M

B

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

DW SUFFIX

CASE 751D−05

ISSUE G

H10X

M

B

M

0.25

D

20

A

11

q

_

E

1

B20X

M

0.25

T

SAS

B

10

B

h X 45

A

L

18X

SEATING

e

A1

T

PLANE

C

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90

q 0 7

__

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7

MC74HC273A

TSSOP−20

PACKAGE DIMENSIONS

DT SUFFIX

CASE 948E−02

ISSUE B

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

L/22X

L

PIN 1 IDENT

110

1120

B

JJ1

−U−

N

S

U0.15 (0.006) T

A

K1

SECTION N−N

0.25 (0.010)

M

−V− N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

SEATING

−T−

PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

MILLIMETERS

−W−

DIMAMIN MAX MIN MAX

B 4.30 4.50 0.169 0.177 C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

6.60 0.260

6.40 0.252

−−− −−−

____

INCHES

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8

MC74HC273A

SOEIAJ−20

PACKAGE DIMENSIONS

F SUFFIX

CASE 967−01

ISSUE O

20

110

Z

D

e

b

0.13 (0.005)

M

11

H

E

A

0.10 (0.004)

M

VIEW P

A

1

NOTES:

L

E

Q

_

L

DETAIL P

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

1

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD

c

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

12.35 12.80 0.486 0.504

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

1.10 1.50 0.043 0.059

E

M

Q

1

Z

10

0

_

0.70 0.90 0.028 0.035

−−− 0.81 −−− 0.032

INCHES

0 _10

_

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9

MC74HC273A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

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MC74HC273A/D

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ON Semiconductor MC74HC273A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual