ON Semiconductor MC74HC245A Technical data

MC74HC245A

2

Octal 3−State Noninverting
Bus Transceiver

High−Performance Silicon−Gate CMOS

The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.

The HC245A is a 3−state noninverting transceiver that is used for
2−way asynchronous communication between data buses. The device

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MARKING

DIAGRAMS

has an active−low Output Enable pin, which is used to place the I/O
ports into high−impedance states. The Direction control determines
whether data flows from A to B or from B to A.

Features

0

1

PDIP−20
N SUFFIX
CASE 738

20

MC74HC245AN

AWLYYWWG

1

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1 mA

• High Noise Immunity Characteristic of CMOS Devices

20

SOIC−20

DW SUFFIX

1

CASE 751D

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Moisture Sensitivity: MSL1 for All Packages

• Chip Complexity: 308 FETs or 77 Equivalent Gates

• Pb−Free Packages are Available*

20

1

TSSOP−20
DT SUFFIX

CASE 948E

20

74HC245A

AWLYYWWG

1

20

HC

245A

ALYWG

G

1

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2005

July, 2005 − Rev. 11

1 Publication Order Number:

20

20

1

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

SOEIAJ−20

F SUFFIX

CASE 967

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)

ORDERING INFORMATION

74HC245A

AWLYWWG

1

MC74HC245A/D

MC74HC245A

T

DIRECTION

A1
A2
A3
A4
A5
A6
A7
A8

GND

Figure 1. Pin Assignment

1
2
3
4
5
6
7
8
9
10

20

V

CC

19

OUTPUT ENABLE

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

11

B8

A

DATA

PORT

DIRECTION

OUTPUT ENABLE

A1
A2
A3
A4
A5
A6
A7
A8

2
3

4
5
6
7
8

9

1

19

FUNCTION TABLE

Control Inputs

Output
Enable

L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (High−Impedance State)

X = don’t c a r e

Direction

Operation

PIN 10 = GND
PIN 20 = V

CC

Figure 2. Logic Diagram

18
17
16
15
14
13
12

B1
B2
B3

B4

B
DATA

B5

POR

B6
B7

11

B8

ORDERING INFORMATION

Device Package Shipping

MC74HC245AN PDIP−20 18 Units / Rail
MC74HC245ANG SOIC−20

(Pb−Free)
MC74HC245ADW SOIC−20 WIDE 38 Units / Rail
MC74HC245ADWG SOIC−20 WIDE

(Pb−Free)
MC74HC245ADWR2 SOIC−20 WIDE 1000 Tape & Reel
MC74HC245ADWR2G SOIC−20 WIDE

(Pb−Free)
MC74HC245ADT TSSOP−20* 75 Units / Rail
MC74HC245ADTG TSSOP−20* 75 Units / Rail
MC74HC245ADTR2 TSSOP−20* 2500 Tape & Reel
MC74HC245ADTR2G TSSOP−20* 2500 Tape & Reel
MC74HC245AF SOEIAJ−20 40 Units / Rail
MC74HC245AFG SOEIAJ−20

(Pb−Free)
MC74HC245AFEL SOEIAJ−20 2000 Tape & Reel
MC74HC245AFELG SOEIAJ−20

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

18 Units / Rail

38 Units / Rail

1000 Tape & Reel

40 Units / Rail

2000 Tape & Reel

†

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2

MC74HC245A

Î

Î

Î

Î

Î

MAXIMUM RATINGS (Note 1)

Symbol

V

V

I

I

T

V

OUT

I

I

OK

OUT

I

CC

GND

STG

T
T

q

P

DC Supply Voltage *0.5 to )7.0 V

CC

DC Input Voltage *0.5 to VCC )0.5 V

IN

DC Output Voltage (Note 2) *0.5 to VCC )0.5 V
DC Input Diode Current $20 mA

IK

DC Output Diode Current $35 mA
DC Output Sink Current $35 mA
DC Supply Current per Supply Pin $75 mA
DC Ground Current per Ground Pin $75 mA
Storage Temperature Range *65 to )150
Lead Temperature, 1 mm from Case for 10 Seconds 260

L

Junction Temperature Under Bias )150

J

Thermal Resistance PDIP

JA

Power Dissipation in Still Air at 85_C PDIP

D

MSL Moisture Sensitivity Level 1

F

V

ESD

I

LATCHUP

Flammability Rating Oxygen Index: 30% to 35% UL 94 V−0 @ 0.125 in

R

ESD Withstand Voltage Human Body Model (Note 3)

Latchup Performance Above VCC and Below GND at 85_C (Note 6)

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.

2. IO absolute maximum rating must observed.

3. Tested to EIA/JESD22−A114−A.

4. Tested to EIA/JESD22−A115−A.

5. Tested to JESD22−C101−A.

6. Tested to EIA/JESD78.

Parameter Value Unit

_C
_C
_C

SOIC

TSSOP

SOIC

TSSOP

Machine Model (Note 4)

Charged Device Model (Note 5)

67
96

128
750

500
450

u2000

u200

u1000

_C/W

mW

V

$300 mA

RECOMMENDED OPERATING CONDITIONS

Symbol

V

Vin, V

T

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types

A

Input Rise and Fall Time VCC = 2.0 V

f

(Figure 3) VCC = 4.5 V

ООООООООООООООООООО

Parameter

VCC = 6.0 V

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3

Min

2.0
0

–55

0
0

ÎÎÎ

0

Max

6.0

V

CC

+125
1000

500

ÎÎ

400

Unit

V

V
_C
ns

Î