MC74HC245A
2
Octal 3−State Noninverting
Bus Transceiver
High−Performance Silicon−Gate CMOS
The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The HC245A is a 3−state noninverting transceiver that is used for
2−way asynchronous communication between data buses. The device
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MARKING
DIAGRAMS
has an active−low Output Enable pin, which is used to place the I/O
ports into high−impedance states. The Direction control determines
whether data flows from A to B or from B to A.
Features
0
1
PDIP−20
N SUFFIX
CASE 738
20
MC74HC245AN
AWLYYWWG
1
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
20
SOIC−20
DW SUFFIX
1
CASE 751D
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Moisture Sensitivity: MSL1 for All Packages
• Chip Complexity: 308 FETs or 77 Equivalent Gates
• Pb−Free Packages are Available*
20
1
TSSOP−20
DT SUFFIX
CASE 948E
20
74HC245A
AWLYYWWG
1
20
HC
245A
ALYWG
G
1
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
July, 2005 − Rev. 11
1 Publication Order Number:
20
20
1
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
SOEIAJ−20
F SUFFIX
CASE 967
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
74HC245A
AWLYWWG
1
MC74HC245A/D
MC74HC245A
T
DIRECTION
A1
A2
A3
A4
A5
A6
A7
A8
GND
Figure 1. Pin Assignment
1
2
3
4
5
6
7
8
9
10
20
V
CC
19
OUTPUT ENABLE
18
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
B8
A
DATA
PORT
DIRECTION
OUTPUT ENABLE
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
1
19
FUNCTION TABLE
Control Inputs
Output
Enable
L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (High−Impedance State)
X = don’t c a r e
Direction
Operation
PIN 10 = GND
PIN 20 = V
CC
Figure 2. Logic Diagram
18
17
16
15
14
13
12
B1
B2
B3
B4
B
DATA
B5
POR
B6
B7
11
B8
ORDERING INFORMATION
Device Package Shipping
MC74HC245AN PDIP−20 18 Units / Rail
MC74HC245ANG SOIC−20
(Pb−Free)
MC74HC245ADW SOIC−20 WIDE 38 Units / Rail
MC74HC245ADWG SOIC−20 WIDE
(Pb−Free)
MC74HC245ADWR2 SOIC−20 WIDE 1000 Tape & Reel
MC74HC245ADWR2G SOIC−20 WIDE
(Pb−Free)
MC74HC245ADT TSSOP−20* 75 Units / Rail
MC74HC245ADTG TSSOP−20* 75 Units / Rail
MC74HC245ADTR2 TSSOP−20* 2500 Tape & Reel
MC74HC245ADTR2G TSSOP−20* 2500 Tape & Reel
MC74HC245AF SOEIAJ−20 40 Units / Rail
MC74HC245AFG SOEIAJ−20
(Pb−Free)
MC74HC245AFEL SOEIAJ−20 2000 Tape & Reel
MC74HC245AFELG SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
18 Units / Rail
38 Units / Rail
1000 Tape & Reel
40 Units / Rail
2000 Tape & Reel
†
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2
MC74HC245A
Î
Î
Î
Î
Î
MAXIMUM RATINGS (Note 1)
Symbol
V
V
I
I
T
V
OUT
I
I
OK
OUT
I
CC
GND
STG
T
T
q
P
DC Supply Voltage *0.5 to )7.0 V
CC
DC Input Voltage *0.5 to VCC )0.5 V
IN
DC Output Voltage (Note 2) *0.5 to VCC )0.5 V
DC Input Diode Current $20 mA
IK
DC Output Diode Current $35 mA
DC Output Sink Current $35 mA
DC Supply Current per Supply Pin $75 mA
DC Ground Current per Ground Pin $75 mA
Storage Temperature Range *65 to )150
Lead Temperature, 1 mm from Case for 10 Seconds 260
L
Junction Temperature Under Bias )150
J
Thermal Resistance PDIP
JA
Power Dissipation in Still Air at 85_C PDIP
D
MSL Moisture Sensitivity Level 1
F
V
ESD
I
LATCHUP
Flammability Rating Oxygen Index: 30% to 35% UL 94 V−0 @ 0.125 in
R
ESD Withstand Voltage Human Body Model (Note 3)
Latchup Performance Above VCC and Below GND at 85_C (Note 6)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.
2. IO absolute maximum rating must observed.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
Parameter Value Unit
_C
_C
_C
SOIC
TSSOP
SOIC
TSSOP
Machine Model (Note 4)
Charged Device Model (Note 5)
67
96
128
750
500
450
u2000
u200
u1000
_C/W
mW
V
$300 mA
RECOMMENDED OPERATING CONDITIONS
Symbol
V
Vin, V
T
tr, t
ÎÎ
DC Supply Voltage (Referenced to GND)
CC
DC Input Voltage, Output Voltage (Referenced to GND)
out
Operating Temperature, All Package Types
A
Input Rise and Fall Time VCC = 2.0 V
f
(Figure 3) VCC = 4.5 V
ООООООООООООООООООО
Parameter
VCC = 6.0 V
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3
Min
2.0
0
–55
0
0
ÎÎÎ
0
Max
6.0
V
CC
+125
1000
500
ÎÎ
400
Unit
V
V
_C
ns
Î
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
ÎÎ
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
Î
l
Î
Î
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
PD
MC74HC245A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
Symbol
V
IH
ÎÎ
ÎÎ
V
IL
ÎÎ
ÎÎ
V
OH
ÎÎ
ÎÎ
ÎÎ
V
OL
ÎÎ
ÎÎ
ÎÎ
I
in
I
OZ
ÎÎ
I
CC
ÎÎ
Minimum High−Level Input Voltage
ОООООООО
ОООООООО
Maximum Low−Level Input Voltage
ОООООООО
ОООООООО
Minimum High−Level Output
Voltage
ОООООООО
ОООООООО
ОООООООО
Maximum Low−Level Output
Voltage
ОООООООО
ОООООООО
ОООООООО
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
ОООООООО
Maximum Quiescent Supply
Current (per Package)
ОООООООО
Parameter
Test Conditions
V
= VCC – 0.1 V
out
|I
| v 20 mA
out
ООООООО
ООООООО
V
= 0.1 V
out
|I
| v 20 mA
out
ООООООО
ООООООО
Vin = V
IH
|I
| v 20 mA
out
ООООООО
Vin = V
IH
ООООООО
Vin = V
IL
|I
| v 20 mA
out
ООООООО
Vin = V
IL
ООООООО
|I
| v 2.4 mA
out
|I
| v 6.0 mA
out
|I
| v 7.8 mA
out
|I
| v 2.4 mA
out
|I
| v 6.0 mA
out
|I
| v 7.8 mA
out
Vin = VCC or GND
Output in High−Impedance Stat e
Vin = VIL or V
ООООООО
V
= VCC or GND
out
IH
Vin = VCC or GND
I
= 0 mA
out
ООООООО
2.0
3.0
Î
4.5
Î
6.0
2.0
3.0
Î
4.5
6.0
Î
2.0
4.5
6.0
Î
3.0
4.5
Î
6.0
2.0
4.5
Î
6.0
3.0
4.5
Î
6.0
6.0
6.0
Î
6.0
Î
7. Information on typical parametric values and high frequency or heavy load considerations can be found in th e ON Semic onductor
High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
ÎÎ
Symbo
t
PLH
ÎÎ
t
PHL
ÎÎ
t
PLZ
t
PHZ
ÎÎ
ÎÎ
t
PZL
t
PZH
ÎÎ
ÎÎ
t
TLH
t
THL
ÎÎ
ОООООООООООООООО
,
Maximum Propagation Delay,
ОООООООООООООООО
A to B, B to A
(Figures 1 and 3)
ОООООООООООООООО
,
Maximum Propagation Delay,
Direction or Output Enable to A or B
ОООООООООООООООО
(Figures 2 and 4)
ОООООООООООООООО
,
Maximum Propagation Delay,
Output Enable to A or B
ОООООООООООООООО
(Figures 2 and 4)
ОООООООООООООООО
,
Maximum Output Transition Time,
Any Output
(Figures 1 and 3)
ОООООООООООООООО
= 50 pF, Input tr = tf = 6 ns)
L
Parameter
V
Î
2.0
Î
3.0
4.5
Î
6.0
2.0
3.0
Î
4.5
Î
6.0
2.0
3.0
Î
4.5
6.0
Î
2.0
3.0
4.5
Î
6.0
C
Maximum Input Capacitance (Pin 1 or Pin 19)
in
C
ÎÎ
Maximum Three−State I/O Capacitance
out
(I/O in High−Impedance State)
ОООООООООООООООО
Î
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
C
9. Used to determine the no−load dynamic power consumption: PD = CPD V
Power Dissipation Capacitance (Per Transceiver Channel) (Note 9)
Semiconductor High−Speed CMOS Data Book (DL129/D).
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2
f + ICC VCC. For load considerations, see the ON
CC
4
–55 to
CC
V
25_C
1.5
2.1
ÎÎ
3.15
ÎÎ
4.2
0.5
0.9
ÎÎ
1.35
1.8
ÎÎ
1.9
4.4
5.9
ÎÎ
2.48
3.98
ÎÎ
5.48
0.1
0.1
ÎÎ
0.1
0.26
0.26
ÎÎ
0.26
± 0.1
± 0.5
ÎÎ
4.0
ÎÎ
Guaranteed Limit
–55 to
CC
25_C
V
75
ÎÎ
55
15
ÎÎ
13
110
90
ÎÎ
22
ÎÎ
19
110
90
ÎÎ
22
19
ÎÎ
60
23
12
ÎÎ
10
−
−
10
15
ÎÎ
Typical @ 25°C, VCC = 5.0 V
v 85_C
1.5
2.1
ÎÎ
3.15
ÎÎ
4.2
0.5
0.9
ÎÎ
1.35
1.8
ÎÎ
1.9
4.4
5.9
ÎÎ
2.34
3.84
ÎÎ
5.34
0.1
0.1
ÎÎ
0.1
0.33
0.33
ÎÎ
0.33
± 1.0
± 5.0
ÎÎ
40
ÎÎ
v 85_C
95
ÎÎ
70
19
ÎÎ
16
140
110
ÎÎ
28
ÎÎ
24
140
110
ÎÎ
28
24
ÎÎ
75
27
15
ÎÎ
13
10
15
ÎÎ
40
v 125_C
v 125_C
1.5
2.1
ÎÎ
3.15
ÎÎ
4.2
0.5
0.9
ÎÎ
1.35
1.8
ÎÎ
1.9
4.4
5.9
ÎÎ
2.2
3.7
ÎÎ
5.2
0.1
0.1
ÎÎ
0.1
0.4
0.4
ÎÎ
0.4
± 1.0
± 10
ÎÎ
160
ÎÎ
110
ÎÎ
80
22
ÎÎ
19
165
130
ÎÎ
33
ÎÎ
28
165
130
ÎÎ
33
28
ÎÎ
90
32
18
ÎÎ
15
10
15
ÎÎ
Unit
V
V
V
V
mA
mA
mA
Unit
ns
ns
ns
ns
pF
pF
pF
INPUT
A OR B
OUTPUT
B OR A
t
PLH
MC74HC245A
V
DIRECTION
t
r
90%
50%
10%
90%
50%
10%
t
TLH
t
f
t
PHL
t
THL
V
CC
GND
OUTPUT
ENABLE
A OR B
A OR B
50%
t
PZLtPLZ
50%
t
PZHtPHZ
50%
50%
10%
90%
CC
GND
V
CC
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
Figure 3. Switching Waveform
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
DEVICE
UNDER
TEST
Figure 4. Switching Waveform
TEST POINT
OUTPUT
1 kW
CONNECT TO VCC WHEN
TESTING t
CONNECT TO GND WHEN
CL*
TESTING t
*Includes all probe and jig capacitance
Figure 6. Test Circuit
PLZ
PHZ
AND t
AND t
PZL
PZH
.
.
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5
A
DATA
PORT
A1
A2
A3
A4
A5
A6
MC74HC245A
2
18
B1
3
17
B2
4
16
B3
5
15
B4
6
14
B5
7
13
B6
B
DATA
PORT
DIRECTION
OUTPUT ENABLE
8
A7
9
A8
1
19
Figure 7. Expanded Logic Diagram
12
11
B7
B8
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6
MC74HC245A
SOIC−20
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
−T−
SEATING
PLANE
−A−
20
11
B
1
10
C
L
K
M
E
FG
N
D 20 PL
0.25 (0.010) T
J 20 PL
M
M
A
0.25 (0.010) T
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
DIM MIN MAX MIN MAX
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
E
F
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
M
B
MILLIMETERSINCHES
1.27 BSC0.050 BSC
1.27 1.770.050 0.070
____
DW SUFFIX
CASE 751D−05
ISSUE G
H10X
M
B
M
0.25
D
20
A
11
q
_
E
1
B20X
M
0.25
T
SAS
B
10
B
h X 45
A
L
18X
SEATING
e
A1
T
PLANE
C
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q 0 7
__
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7
MC74HC245A
TSSOP−20
PACKAGE DIMENSIONS
DT SUFFIX
CASE 948E−02
ISSUE B
20X REFK
S
U0.15 (0.006) T
0.10 (0.004) V
M
S
U
T
S
K
L/22X
L
PIN 1
IDENT
110
1120
B
JJ1
−U−
N
S
U0.15 (0.006) T
A
K1
SECTION N−N
0.25 (0.010)
M
−V−
N
F
DETAIL E
C
G
H
DETAIL E
0.100 (0.004)
SEATING
−T−
PLANE
D
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
−W−
DIMAMIN MAX MIN MAX
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
6.60 0.260
6.40 0.252
−−− −−−
____
INCHES
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8
MC74HC245A
SOEIAJ−20
PACKAGE DIMENSIONS
F SUFFIX
CASE 967−01
ISSUE O
20
110
Z
D
e
b
0.13 (0.005)
M
11
H
E
E
A
A
0.10 (0.004)
M
VIEW P
1
NOTES:
L
E
Q
_
L
DETAIL P
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
1
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
c
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
−−− 2.05 −−− 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
12.35 12.80 0.486 0.504
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
L
L
1.10 1.50 0.043 0.059
E
M
Q
1
Z
10
0
_
0.70 0.90 0.028 0.035
−−− 0.81 −−− 0.032
INCHES
0 _10
_
_
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MC74HC245A
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MC74HC245A/D
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