ON Semiconductor MC74HC244A Technical data

MC74HC244A

2

Octal 3−State Noninverting Buffer/Line Driver/ Line Receiver

High−Performance Silicon−Gate CMOS

The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This octal noninverting buffer/line driver/line receiver is designed

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MARKING

DIAGRAMS

to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The device has noninverting outputs and two active−low output enables.

The HC244A is similar in function to the HC240A.

Features

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1 mA

20

0

1

PDIP−20 N SUFFIX CASE 738

SOIC−20

DW SUFFIX CASE 751D

• High Noise Immunity Characteristic of CMOS Devices

20

MC74HC244AN

AWLYYWWG

1

20

74HC244A

AWLYYWWG

1

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 136 FETs or 34 Equivalent Gates

• Pb−Free Packages are Available*

20

TSSOP−20 DT SUFFIX

1

CASE 948E

20

HC

244A

ALYWG

G

1

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

July, 2005 − Rev. 10

1 Publication Order Number:

20

1

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

SOEIAJ−20

F SUFFIX

CASE 967

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location)

ORDERING INFORMATION

74HC244A

AWLYWWG

1

MC74HC244A/D

MC74HC244A

PIN ASSIGNMENT

ENABLE A

A1

YB4

A2

YB3 5

A3

YB2

A4

YB1

GND

1

2

3

4

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

FUNCTION TABLE

Inputs Outputs

Enable A, Enable B A, B YA, YB

LLL LHH

HXZ

Z = high impedance

V

CC

ENABLE B

YA1

B4

YA2

B3

YA3

B2

YA4

B1

DATA

INPUTS

OUTPUT

ENABLES

LOGIC DIAGRAM

218

A1

4

A2

6

A3

8

A4

11

B1

13

B2

15

B3

17

B4

ENABLE A ENABLE B

1 19

YA1

16

YA2

14

YA3

12

YA4

9

YB1

7

YB2

5

YB3

3

YB4

PIN 20 = V PIN 10 = GND

CC

NONINVERTING OUTPUTS

ORDERING INFORMATION

Device Package Shipping

MC74HC244AN PDIP−20 18 Units / Rail MC74HC244ANG SOIC−20

(Pb−Free) MC74HC244ADW SOIC−20 WIDE 38 Units / Rail MC74HC244ADWG SOIC−20 WIDE

(Pb−Free) MC74HC244ADWR2 SOIC−20 WIDE 1000 Tape & Reel MC74HC244ADWR2G SOIC−20 WIDE

(Pb−Free) MC74HC244ADT TSSOP−20* 75 Units / Rail MC74HC244ADTG TSSOP−20* 75 Units / Rail MC74HC244ADTR2 TSSOP−20* 2500 Tape & Reel MC74HC244ADTR2G TSSOP−20* 2500 Tape & Reel MC74HC244AF SOEIAJ−20 40 Units / Rail MC74HC244AFG SOEIAJ−20

(Pb−Free) MC74HC244AFEL SOEIAJ−20 2000 Tape & Reel MC74HC244AFELG SOEIAJ−20

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

18 Units / Rail

38 Units / Rail

1000 Tape & Reel

40 Units / Rail

2000 Tape & Reel

†

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2

MC74HC244A

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

MAXIMUM RATINGS

Symbol

V

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

T

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

(Plastic DIP, SOIC, SSOP or TSSOP Package)

ОООООООООООО

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 35 ± 75

750 500

ÎÎÎ

450

– 65 to + 150

260

ÎÎÎ

Unit

mA mA mA

mW

Î

_C _C

This device contains protection

V V V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

) v VCC.

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

T

A

tr, t

f

ÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

ОООООООООООО

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

VCC = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol

ÎÎ

V

IH

ÎÎ

V

IL

ÎÎ

V

OH

ÎÎ

V

OL

ÎÎ

ОООООООО

Minimum High−Level Input Voltage

ОООООООО

Maximum Low−Level Input Voltage

ОООООООО

Minimum High−Level Output Voltage

ОООООООО

Maximum Low−Level Output

ОООООООО

Voltage

ОООООООО

Parameter

Test Conditions

ООООООО

V

= VCC – 0.1 V

out

|I

| v 20 mA

out

ООООООО

V

= 0.1 V

out

ООООООО

|I

| v 20 mA

out

ООООООО

Vin = V

IH

|I

| v 20 mA

out

ООООООО

Vin = V

IH

ООООООО

Vin = V

IL

ООООООО

|I

| v 20 mA

out

ООООООО

Vin = V

IL

ООООООО

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Min

2.0 0

– 55

0 0 0

|I |I |I

3

out out out

Max

6.0

V

CC

+ 125

1000

ÎÎ

500 400

ÎÎ

| v 2.4 mA | v 6.0 mA | v 7.8 mA

Unit

V V

_C

ns

Î

V

Î

2.0

3.0

Î

4.5

6.0

2.0

Î

3.0

4.5

Î

6.0

2.0

4.5

Î

6.0

3.0

4.5

Î

6.0

2.0

Î

4.5

6.0

Î

3.0

4.5

6.0

Î

CC

V

Guaranteed Limit

– 55 to

25_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

4.4

ÎÎ

5.9

2.48

3.98

ÎÎ

5.48

0.1

ÎÎ

0.1

ÎÎ

0.26

ÎÎ

v 85_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

4.4

ÎÎ

5.9

2.34

3.84

ÎÎ

5.34

0.1

ÎÎ

0.1

ÎÎ

0.33

ÎÎ

v 125_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

4.4

ÎÎ

5.9

2.2

3.7

ÎÎ

5.2

0.1

ÎÎ

0.1

ÎÎ

0.4

ÎÎ

Unit

V

MC74HC244A

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

l

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

6.0

CC

– 55 to

25_C

± 0.1 ± 0.5

ÎÎ

4.0

ÎÎ

v 85_C

± 1.0 ± 5.0

ÎÎ

40

ÎÎ

v 125_C

± 1.0

± 10

ÎÎ

160

ÎÎ

Unit

mA mA

mA

V

Symbol

I

in

I

OZ

ÎÎ

I

CC

ÎÎ

Parameter

Maximum Input Leakage Current Maximum Three−State Leakage

Current

ОООООООО

Maximum Quiescent Supply Current (per Package)

ОООООООО

Vin = VCC or GND Output in High−Impedance State

Vin = VIL or V V

Vin = VCC or GND I

Test Conditions

ООООООО

= VCC or GND

out

= 0 mA

ООООООО

out

IH

Î

NOTE: Infor matio n on typ ical p arame tric value s and high frequency or heavy load considerations can be f ound in Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6 ns)

L

Guaranteed Limit

ÎÎ

Symbo

t

PLH

ÎÎ

t

PHL

ÎÎ

t

PLZ

ÎÎ

t

PHZ

ÎÎ

t

PZL

ÎÎ

t

PZH

ÎÎ

t

TLH

ÎÎ

t

THL

ÎÎ

C

in

C

out

ÎÎ

ОООООООООООООООО

Parameter

,

Maximum Propagation Delay, A to YA or B to YB

ОООООООООООООООО

(Figures 1 and 3)

ОООООООООООООООО

,

Maximum Propagation Delay, Output Enable to YA or YB

ОООООООООООООООО

(Figures 2 and 4)

ОООООООООООООООО

,

Maximum Propagation Delay, Output Enable to YA or YB

ОООООООООООООООО

(Figures 2 and 4)

ОООООООООООООООО

,

Maximum Output Transition Time, Any Output

ОООООООООООООООО

(Figures 1 and 3)

ОООООООООООООООО

Maximum Input Capacitance Maximum Three−State Output Capacitance

(Output in High−Impedance State)

ОООООООООООООООО

V

Î

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

CC

−

– 55 to

25_C

96

ÎÎ

50 18

ÎÎ

15

110

ÎÎ

60 22

ÎÎ

19

110

ÎÎ

60 22

ÎÎ

19 60

ÎÎ

23 12

ÎÎ

10 10 15

ÎÎ

v85_C

115

ÎÎ

60 23

ÎÎ

20

140

ÎÎ

70 28

ÎÎ

24

140

ÎÎ

70 28

ÎÎ

24 75

ÎÎ

27 15

ÎÎ

13 10 15

ÎÎ

v125_C

135

ÎÎ

70 27

ÎÎ

23

165

ÎÎ

80 33

ÎÎ

28

165

ÎÎ

80 33

ÎÎ

28 90

ÎÎ

32 18

ÎÎ

15 10 15

ÎÎ

Unit

ns

pF pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

C

Power Dissipation Capacitance (Per Buffer)*

PD

*Used to determine t he no−load d ynamic p ower consumption: PD = CPD V

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

CC

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4

Typical @ 25°C, VCC = 5.0 V

34

2

f + ICC VCC. For load considerations, see Chapter 2 of t h e

pF

MC74HC244A

SWITCHING WAVEFORMS

t

PLH

r

90%

50%

10%

90%

50%

10%

t

TLH

DATA INPUT

A OR B

OUTPUT

YA OR YB

Figure 1. Figure 2.

OUTPUT

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

TEST POINT

CL*

t

f

t

PHL

V

CC

GND

t

THL

ENABLE

A OR B

OUTPUT Y

50%

t

PZL

50%

t

PZHtPHZ

50%

t

PLZ

10%

90%

V

CC

GND

HIGH IMPEDANCE

V

OL

V

OH

HIGH IMPEDANCE

TEST CIRCUITS

TEST POINT

CONNECT TO VCC WHEN TESTING t CONNECT TO GND WHEN TESTING t

PLZ

PHZ

AND t

PZL

PZH

.

DEVICE UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

1 kW

CL*

Figure 3. Test Circuit

PIN DESCRIPTIONS

INPUTS A1, A2, A3, A4, B1, B2, B3, B4

(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled.

CONTROLS Enable A, Enable B (Pins 1, 19)

Output enables (active−low). When a low level is applied to these pins, the outputs are enabled and the devices

Figure 4. Test Circuit

function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state.

OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4

(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Device outputs. Depending upon the state of the output−enable pins, these outputs are either noninverting outputs or high−impedance outputs.

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5

DATA

INPUT

A OR B

ENABLE A OR

ENABLE B

MC74HC244A

LOGIC DETAIL

TO THREE OTHER

A OR B INVERTERS

ONE OF 8

INVERTERS

V

CC

YA OR YB

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6

MC74HC244A

SOIC−20

PACKAGE DIMENSIONS

PDIP−20

N SUFFIX

PLASTIC DIP PACKAGE

CASE 738−03

ISSUE E

−T−

SEATING PLANE

−A−

20

11

B

1

10

C

L

K

M

E

FG

N

D 20 PL

0.25 (0.010) T

J 20 PL

M

A

0.25 (0.010) T

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022 E F G 2.54 BSC0.100 BSC

J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC M 0 15 0 15 N 0.51 1.010.020 0.040

M

B

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

DW SUFFIX

CASE 751D−05

ISSUE G

H10X

M

B

M

0.25

D

20

A

11

q

_

E

1

B20X

M

0.25

T

10

SAS

B

h X 45

A

L

18X

SEATING

e

A1

T

PLANE

C

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90

q 0 7

__

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7

MC74HC244A

TSSOP−20

PACKAGE DIMENSIONS

DT SUFFIX

CASE 948E−02

ISSUE B

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

L/22X

L

PIN 1 IDENT

110

1120

B

JJ1

−U−

N

S

U0.15 (0.006) T

A

K1

SECTION N−N

0.25 (0.010)

M

−V− N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

SEATING

−T−

PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

MILLIMETERS

−W−

DIMAMIN MAX MIN MAX

B 4.30 4.50 0.169 0.177 C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

6.60 0.260

6.40 0.252

−−− −−−

____

INCHES

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8

MC74HC244A

SOEIAJ−20

PACKAGE DIMENSIONS

F SUFFIX

CASE 967−01

ISSUE O

20

110

Z

D

e

b

0.13 (0.005)

M

11

H

E

A

0.10 (0.004)

M

VIEW P

A

1

NOTES:

L

E

Q

_

L

DETAIL P

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

1

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD

c

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

12.35 12.80 0.486 0.504

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

1.10 1.50 0.043 0.059

E

M Q

1

Z

10

0

_

0.70 0.90 0.028 0.035

−−− 0.81 −−− 0.032

INCHES

0 _10

_

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9

MC74HC244A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MC74HC244A/D

10

ON Semiconductor MC74HC244A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual