ON Semiconductor MC74HC04A Technical data

MC74HC04A

Hex Inverter

High−Performance Silicon−Gate CMOS

The MC74HC04A is identical in pinout to the LS04 and the MC14069. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The device consists of six three−stage inverters.

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1 A

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 36 FETs or 9 Equivalent Gates

• Pb−Free Packages are Available*

LOGIC DIAGRAM

Y1A1

Y = A

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PDIP−14

N SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14 DT SUFFIX

CASE 948G

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MARKING

DIAGRAMS

MC74HC04AN

AWLYYWW

HC04A

AWLYWW

ALYW

Pinout: 14−Lead Packages (Top View)

A6 Y6 A5 Y5 A4 Y4

1314 12 11 10 9 8

21 34567

A1 Y1 A2 Y2 A3 Y3 GND

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

May, 2005 − Rev. 10

1 Publication Order Number:

FUNCTION TABLE

Inputs Outputs

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

MC74HC04A/D

MC74HC04A

ОООООООООООООООООООООО

†

MAXIMUM RATINGS

Symbol

out

ÎÎÎ

stg

ÎÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP†

ОООООООООООООООООООО

Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds

ОООООООООООООООООООО

Plastic DIP, SOIC or TSSOP Package

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be

taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V V

should be constrained to the range GND  (Vin or V

out

(e.g., either GND or V

†Derating − Plastic DIP: – 10 mW/C from 65 to 125C

). Unused outputs must be left open.

SOIC Package: – 7 mW/C from 65 to 125C TSSOP Package: − 6.1 mW/C from 65 to 125C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 25 ± 50

750

SOIC Package†

TSSOP Package†

ÎÎÎÎ

500 450

ÎÎÎÎ

– 65 to + 150

ÎÎÎÎ

260

)  VCC. Unused inputs must always be tied to an appropriate logic voltage level

out

Unit

mA mA mA

C C

V V V

and

RECOMMENDED OPERATING CONDITIONS

Symbol

Vin, V

out

tr, t

ÎÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

(Figure 1) V

ОООООООООООООООООООО

Parameter

= 4.5 V = 6.0 V

Min

2.0 0

– 55

0 0

Max

6.0

+ 125

1000

500

ÎÎ

400

Unit

V V

C

ORDERING INFORMATION

Device Order Number Package Shipping

MC74HC04AN PDIP−14 2000 / Rail MC74HC04ANG PDIP−14

(Pb−Free) MC74HC04AD SOIC−14 55 / Rail MC74HC04ADG SOIC−14

(Pb−Free) MC74HC04ADR2 SOIC−14 2500 / Tape & Reel MC74HC04ADR2G SOIC−14

(Pb−Free) MC74HC04ADTR2 TSSOP−14* 2500 / Tape & Reel MC74HC04AF SOEIAJ−14 50 / Rail MC74HC04AFG SOEIAJ−14

(Pb−Free) MC74HC04AFEL SOEIAJ−14 2000 / Tape & Reel MC74HC04AFELG SOEIAJ−14

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

2000 / Rail

55 / Rail

2500 / Tape & Reel

50 / Rail

2000 / Tape & Reel

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MC74HC04A

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Parameter Condition

Minimum High−Level Input Voltage

= 0.1V or VCC −0.1V

out

| ≤ 20A

out

2.0

3.0

4.5

6.0

Maximum Low−Level Input Voltage

= 0.1V or VCC − 0.1V

out

| ≤ 20A

out

2.0

3.0

4.5

6.0

Minimum High−Level Output Voltage

Vin = VIH or V |I

| ≤ 20A

out

2.0

4.5

6.0

Vin =VIH or V

Maximum Low−Level Output Voltage

Vin = VIH or V |I

| ≤ 20A

out

| ≤ 2.4mA | ≤ 4.0mA | ≤ 5.2mA

3.0

4.5

6.0

2.0

4.5

6.0

Vin = VIH or V

Maximum Input Leakage

Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 A

out

| ≤ 2.4mA | ≤ 4.0mA | ≤ 5.2mA

3.0

4.5

6.0

Current

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND I

= 0A

out

6.0 1.0 10 40 A

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor H igh−Speed CMOS D ata B ook (DL129/D).

Guaranteed Limit

−55 to 25°C ≤85°C ≤125°C Unit

1.50

2.10

3.15

4.20

0.50

0.90

1.35

1.80

1.9

4.4

5.9

2.48

3.98

5.48

0.1

0.26

1.50

2.10

3.15

4.20

0.50

0.90

1.35

1.80

1.9

4.4

5.9

2.34

3.84

5.34

0.1

0.33

1.50

2.10

3.15

4.20

0.50

0.90

1.35

1.80

1.9

4.4

5.9

2.20

3.70

5.20

0.1

0.40

AC CHARACTERISTICS (C

Symbol Parameter

PLH PHL

TLH

THL

Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2)

Maximum Output Transition Time, Any Output (Figures 1 and 2)

Maximum Input Capacitance 10 10 10 pF

= 50pF, Input tr = tf = 6ns)

−55 to 25°C ≤85°C ≤125°C Unit

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

Guaranteed Limit

75 30 15 13

75 27 15 13

95 40 19 16

95 32 19 16

110

55 22 19

110

36 22 19

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

Power Dissipation Capacitance (Per Inverter)*

*Used to determine the no−load dynamic power consumption: PD = CPD V

f + ICC VCC. For load considerations, see Chapter 2 of t h e

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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INPUT A

OUTPUT Y

90%

50%

10%

PLH

MC74HC04A

90%

50%

10%

GND

PHL

TLH

Figure 1. Switching Waveforms

TEST

POINT

OUTPUT

DEVICE

UNDER

TEST

CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

THL

Figure 3. Expanded Logic Diagram

(1/6 of the Device Shown)

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−T−

SEATING PLANE

14 8

MC74HC04A

PACKAGE DIMENSIONS

PDIP−14

N SUFFIX

CASE 646−06

ISSUE N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

14 PL

0.13 (0.005)

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 18.80 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L

0.290 0.310 7.37 7.87

M −−− 10 −−− 10

N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES



−T−

SEATING PLANE

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE G

−A−

D 14 PL

0.25 (0.010) A

−B−

7 PL

0.25 (0.010) B

X 45



NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL

CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

 

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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MC74HC04A

PACKAGE DIMENSIONS

TSSOP−14 DT SUFFIX

CASE 948G−01

ISSUE A

0.10 (0.004)

−T−

SEATING PLANE

14X REFK

0.25 (0.010)

U0.15 (0.006) T

2X L/2

0.10 (0.004) V

PIN 1 IDENT.

U0.15 (0.006) T

−V−

−U− F

DETAIL E

SECTION N−N

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024

−W−

J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8



INCHESMILLIMETERS

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MC74HC04A/D

ON Semiconductor MC74HC04A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual