ON Semiconductor MC34271 Technical data

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MC34271

Liquid Crystal Display and
Backlight Integrated
Controller

The MC34271 is a low power dual switching voltage regulator,
specifically designed for handheld and laptop applications, to provide
several regulated output voltages using a minimum of external parts.
Two uncommitted switching regulators feature a very low standby
bias current of 5.0 µA, and an operating current of 7.0 mA capable of
supplying output currents in excess of 200 mA.

Both devices have three additional features. The first is an ELD
Output that can be used to drive a backlight or a liquid crystal display .
The ELD output frequency is the clock divided by 256. The second
feature allows four additional output bias voltages, in specific
proportions to VB, one of the switching regulated output voltages. It
allows use of mixed logic circuitry and provides a voltage bias for
N–Channel load control MOSFETst. The third feature is an Enable
input that allows a logic level signal to turn–“off” or turn–“on” both
switching regulators.

Due to the low bias current specifications, this device is ideally
suited for battery powered computer, consumer, and industrial
equipment where an extension of useful battery life is desirable.

MC34271 Features:

• Low Standby Bias Current of 5.0 µA

• Uncommitted Switching Regulators Allow Both Positive and

Negative Supply Voltages

• Logic Enable Allows Microprocessor Control of All Outputs

• Synchronizable to External Clock

• Mode Commandable for ELD and LCD Interface

• Frequency Synchronizable

• Auxiliary Output Bias Voltages Enable Load Control via N–Channel

FETs

MAXIMUM RATINGS (T

Rating

Input Voltage
Power Dissipation and

Thermal Characteristics

Maximum Power Dissipation – Case 873 P
Thermal Resistance, Junction–to–Ambient R

Thermal Resistance, Junction–to–Case R
Output #1 and #2 Switch Current
Output #1 and #2 “Off”–State V oltage
Feedback Enable MOSFETs

“Off”–State Voltage
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature Range

= 25°C, unless otherwise noted.)

A

Symbol Value Unit

V

DD

D

θJA
θJC

ISL & I

SB

V

SL

V

LF

T

J

T

A

T

stg

16

1.43 W
100 °C/W

60 °C/W

500

60
20

125

0 to +70

–55 to +150

Vdc

mA
Vdc
Vdc

°C
°C
°C

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32

1

QFP–32

FB SUFFIX

CASE 873

PIN CONNECTIONS AND

MARKING DIAGRAM

32

31 30 29 2728 26 25

1

T

SW

124

DS

1

2

Ref

1

3

FB

1

4

Comp

1

5

SS

1

6

S

1

7

D

1

8

Drv

1

ELD

9101112 1413 15 16

R

Sync

Mode

V

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

Gnd

AWLYYWW

DD

4

V

(Top View)

A

V

MC34271

3

V

1

ref

V

EN

DS

Ref

Comp

SS

V2V1V

FB

V

EN

S
D

0

2

2

23

2

22

2

21

2

20

2

19

2

18

2

17

B

ORDERING INFORMATION

Device Package Shipping

MC34271FB QFP–32 250 Units / Tray

 Semiconductor Components Industries, LLC, 2000

April, 2000 – Rev. 0

1 Publication Order Number:

MC34271/D

EL

Panel

From DAC

EL

Control

µP Control

V

B

V

in

On/Off

Comp

Comp

VA = 5.0 V

MC34271

Representative Block Diagram

SW

EN

Drv

Sync

R

V

Ref

Ref

FB

EN

Ref

FB

1

32

1

26

1

8

31

30

T

V

27

1.25 V

1

2

1

3

1

4

2

25

2

23

2

22

2

21

28

÷ 2

ref

V

DD

BIAS

OSC

Circuit #1

PWM

Circuit #2

ELD

EN

PWM

BIAS Output

Buffers

D

1

7

S

1

6

ELD

9

V

V

DD

DD

11

Mode

10

D

2

18

S

2

19

V

B

17

V

0

16

V

1

15

V

2

14

V

3

13

V

in

V

B

V

0

V

1

V

2

V

3

Gnd

29

This device contains 350 active transistors.

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2

V

4

12

V

4

MC34271

ELECTRICAL CHARACTERISTICS (V

the operating ambient temperature range that applies, unless otherwise noted.)

Characteristic

REFERENCE SECTION

Reference Voltage (TJ = 25°C) V
Line Regulation (VDD = 5.0 V to 12.5 V) Reg
Load Regulation (IO = 0 to 120 µA) Reg
Total Variation (Line, Load and Temperature) V

ERROR AMPLIFIERS

Input Offset Voltage (VCM = 1.25 V) V
Input Bias Current (VCM = 1.25 V) I
Open Loop Voltage Gain (VCM = 1.25 V, V
Output Voltage Swing V

High State (IOH = –100 µA) Ve
Low State (IOL = 100 µA) Ve

BIAS VOLTAGE

Voltage (VDD = 5.0 V to 12.5 V, IO = 0) V

OSCILLATOR AND PWM SECTIONS

Total Frequency Variation Over Line and Temperature f

VDD = 5.0 V to 10 V, TA = 0° to 70°C, RT = 169 k 90 115 140

Duty Cycle at Each Output %

Maximum DC
Minimum DC

Sync Input

Input Resistance (V
Minimum Sync Pulse Width T

OUTPUT MOSFETs

Output Voltage – “On”–State (I
Output Current – “Off”–State (VOH = 40 V) I
Rise and Fall Times tr, t

EL DISCHARGE OUTPUT (ELD) AND DRV

Output Voltage – “On”–State (I
Output Voltage – “On”–State (I
Output Voltage – “Off”–State (I
Output Voltage – “Off”–State (I

FEEDBACK ENABLE SWITCHES (DS1, DS2)

Output Voltage – “Low”–State (I
Output Current – “Off”–State (VOH = 12.5 V) Ife

SWITCHED VDD OUTPUT (SW1)

Output Voltage V

Switch “On” (EN1 = 1, I
Switch “Off” (EN1 = 0, I

AUXILIARY VOLTAGE OUTPUTS

V0 Enable Switch

“On”–Resistance: VB to V
“Off”–State Leakage Current (VB = 10 V) I
V0 Voltage (VB = 30 V, I
V0 Resistance (I

NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

= 3.5 V) R

sync

= 200 mA) V

sink

= 100 µA) V

sink

= 50 mA) V

sink

= –100 µA) V

source

= –50 mA) V

source

= 1.0 mA) Vfe

sink

= 100 µA) Vsw

source

= 100 µA) Vsw

sink

0

= 0 mA) V

source

= 4.0 mA) R

source

= 6.0 V, for typical values TA = Low to High [Note 1], for min/max values TA is

DD

Symbol Min Typ Max Unit

1.225 1.250 1.275 V
– 2.0 10 mV
– 2.0 10 mV

1.215 – 1.285 V

– 1.0 10 mV
– 120 600 nA

80 100 – dB

VA–1.5 4.0 5.5

0 – 1.0

4.6 5.0 5.4 V

92 95 –

– – 0

25 50 100 kΩ

– 1.0 – µs

– 150 250 mV
– 0.1 1.0 µA
– 50 – ns

– 30 100 mV
– 2.0 2.5 V

VDD–0.5 5.9 – V
VDD–3.5 3.3 – V

– 10 100 mV
– 0.6 1.0 µA

5.5 5.9 6.0
0 0.1 0.2

0 0.1 2.0 µA

29.5 29.9 30 V
20 40 60 Ω

= 2.0 V) A

COMP

1

ref

line

load

ref

IO
IB

VOL

OH

OL

A

OSC

max

min

sync

p

OL

OH

f

OL

OL
OH
OH

OL

OH

OH

OL

Rds 0 2.0 10 Ω

lkg

0

0

kHz

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3

MC34271

100

1.0

DC

SWITC

O

T

T

D

T

C

CLE

0

ELECTRICAL CHARACTERISTICS (continued) (V

the operating ambient temperature range that applies, unless otherwise noted.)

Characteristic UnitMaxTypMinSymbol

AUXILIARY VOLTAGE OUTPUTS

V1, V2, V3, V4 Outputs

1–V1/V0 Ratio 0.0500 0.0520 0.0535
1–V2/V0 Ratio 0.1010 0.1035 0.1065

V3/V0 Ratio 0.1010 0.1035 0.1065

V4/V0 Ratio 0.0500 0.0520 0.0535
Output Resistance (I
Output Short Circuit Current I

LOGIC INPUTS (EN1, EN2, MODE)

Input Low State V
Input High State V
Input Impedance R

SOFT START CONTROL (SS1,SS2)

Charge Current (Capacitor Voltage = 1.0 V to 4.0 V)

Discharge Current (Capacitor Voltage = 1.0 V) I

TOTAL SUPPLY CURRENT

VDD Current VDD = 6.0 V I

Standby Mode (EN1 = EN2 = 0) VDD = 16 V – 3.0 15

VDD Current I

Backlight “On” (EN1 = 1; EN2 = 0)

VDD Current I

LCD “On” (No Inductor) (EN1 = 0; EN2 = 1)

VB Current (V0 = 35 V) I

NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

= 4.0 mA) R

source

= 6.0 V , for typical values TA = Low to High [Note 1], for min/max values TA is

DD

o

ss

IL

IH

in

I

chg

dschg

CC

CC

CC

O

20 40 60 Ω

5.0 10 20 mA

0 – 0.8 V

2.0 – 6.0 V
25 50 100 kΩ

0.5 1.0 2.5 µA

250 650 – µA

– 2.0 5.0 µA

– 0.7 3.0 mA

– 0.9 2.0 mA

– 1.2 3.0 mA

Y
Y

U
PU

U
H

,

0.8

0.6

0.4

0.2

0

1.5

2.0 2.5 3.0 3.5 4.0 4.5 100 1.0 k 10 k 100 k 1000 k
V

, COMPENSATION VOLTAGE (V)

Comp

Figure 1. Switch Output Duty Cycle versus

Compensation V oltage

VDD = 6.0 V
TA = 25°C

80

60

40

20

, OPEN LOOP VOLTAGE GAIN (dB)

0

VOL

A

–20

10

Figure 2. Error Amp Open Loop Gain and

Gain

Phase

f, FREQUENCY (Hz)

Phase versus Frequency

VDD = 6.0 V
V

Comp

RL = Open
TA = 25°C

= 2.5 V

30

60

90

120

150

180

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