ON Semiconductor MC14553B Technical data

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MC14553B

3-Digit BCD Counter

The MC14553B 3–digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.

An on–chip oscillator provides the low–frequency scanning clock
which drives the multiplexer output selector.

This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.

• TTL Compatible Outputs

• On–Chip Oscillator

• Cascadable

• Clock Disable Input

• Pulse Shaping Permits Very Slow Rise Times on Input Clock

• Output Latches

• Master Reset

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16

PDIP–16

P SUFFIX

CASE 648

SOIC–16
DW SUFFIX
CASE 751G

MARKING

DIAGRAMS

MC14553BCP

AWLYYWW

1

16

14553B

AWLYYWW

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

DD

Vin, V

I

in

I

out

P

T

T

stg

T

1. Maximum Ratings are those values beyond which damage to the device
may occur.

2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range

out

D

A

L

(DC or Transient)

Input Current

(DC or Transient) per Pin

Output Current

(DC or Transient) per Pin

Power Dissipation,

per Package (Note 2.)
Ambient Temperature Range –55 to +125 °C
Storage Temperature Range –65 to +150 °C
Lead Temperature

(8–Second Soldering)

v (Vin or V

SS

or VDD). Unused outputs must be left open.

SS

) v VDD.

out

) (Note 1.)

SS

–0.5 to VDD + 0.5 V

±10 mA

+20 mA

500 mW

260 °C

and V

in

should be constrained

out

1

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

ORDERING INFORMATION

Device Package Shipping

MC14553BCP PDIP–16 25/Rail
MC14553BDW SOIC–16 47/Rail

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14553B/D

MC14553B

BLOCK DIAGRAM

43

CIA CIB

12

10

13

CLOCK

LE

11

DIS

MR

V

= PIN 16

DD

V

SS

Q0
Q1

Q2
Q3

O.F.
DS
DS
DS

= PIN 8

9
7
6
5
14

1

2
1

2
3

15

TRUTH TABLE

Inputs

Master

Reset

0 0 0 No Change
0 0 0 Advance
0 X 1 X No Change
0 1 0 Advance
0 1 0 No Change
0 0 X X No Change
0 X X Latched
0 X X 1 Latched
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0

X = Don’t Care

Clock Disable LE

Outputs

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2

MC14553B

V

DD

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic Symbol

Output Voltage “0” Level

V

= VDD or 0

in

“1” Level

V

= 0 or V

in

DD

Input Voltage “0” Level

(V

= 4.5 or 0.5 Vdc)

O

(V

= 9.0 or 1.0 Vdc)

O

(V

= 13.5 or 1.5 Vdc)

O

“1” Level

(V

= 0.5 or 4.5 Vdc)

O

= 1.0 or 9.0 Vdc)

(V

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 4.6 Vdc) Source —

OH

= 9.5 Vdc) Pin 3

(V

OH

(V

= 13.5 Vdc)

OH

(VOH = 4.6 Vdc) Source —
(V

= 9.5 Vdc) Other

OH

= 13.5 Vdc) Outputs

(V

OH

(VOL = 0.4 Vdc) Sink —
(V

= 0.5 Vdc) Pin 3

OL

= 1.5 Vdc)

(V

OL

(VOL = 0.4 Vdc) Sink — Other
(V

= 0.5 Vdc) Outputs

OL

= 1.5 Vdc)

(V

OL

Input Current I
Input Capacitance

(V

= 0)

in

Quiescent Current

(Per Package)

MR = V

DD

Total Supply Current

(4.) (5.)

(Dynamic plus Quiescent,
Per Package)

= 50 pF on all outputs, all

(C

L

V

OL

V

OH

V

V

I

OH

I

OL

in

C

I

DD

I

Vdc

5.0
10
15

5.0
10
15

IL

5.0
10
15

IH

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

Min Max Min Typ

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 0.25
– 0.62

– 1.8

– 0.64

– 1.6
– 4.2

0.5

1.1

1.8

3.0

6.0
18

15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

in

T

— — — — 5.0 7.5 — — pF

5.0
10
15

—
—
—

5.0
10
15

)

SS

– 55_C 25_C 125_C

(3.)

Max Min Max

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

5.0
10
20

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 0.2
– 0.5
– 1.5

– 0.51

– 1.3
– 3.4

0.4

0.9

1.5

2.5

5.0
15

—
—
—

0
0
0

5.0
10
15

2.25

4.50

6.75

2.75

5.50

8.25

– 0.36

– 0.9
– 3.5

– 0.88
– 2.25

– 8.8

0.88

2.25

8.8

4.0

8.0
20

0.010

0.020

0.030

IT = (0.35 µA/kHz) f + I
IT = (0.85 µA/kHz) f + I
IT = (1.50 µA/kHz) f + I

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

5.0
10
20

DD
DD
DD

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

0.14

0.35

1.1

– 0.36

– 0.9
– 2.4

0.28

0.65

1.20

1.6

3.5
10

—
—
—

0.05

0.05

0.05

buffers switching)

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF:
I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

T

—
—
—

1.5

3.0

4.0

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

150
300
600

Unit

Vdc

Vdc

Vdc

Vdc

mAdc

mAdc

mAdc

mAdc

µAdc

µAdc

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3

MC14553B

SWITCHING CHARACTERISTICS

Characteristic

Output Rise and Fall Time

t

, t

TLH

t

TLH

t

TLH

Clock to BCD Out 2a t

Clock to Overflow 2a t

Reset to BCD Out 2b t

Clock to Latch Enable Setup Time
Master Reset to Latch Enable Setup Time

Removal Time

Latch Enable to Clock

Clock Pulse Width 2a t

Reset Pulse Width 2b t

Reset Removal Time — t

Input Clock Frequency 2a f

Input Clock Rise Time 2b t

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

(6.)

(C

= 50 pF, TA = 25_C)

L

Figure Symbol V

2a t

2b t

2b t

TLH

t

THL

PLH

t

PHL

PHL

PHL

su

rem

WH(cl)

WH(R)

rem

cl

TLH

DD

Min Typ

(7.)

Max Unit

,

5.0
10
15

,

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10

—
—
—

—
—
—

—
—
—

—
—
—

600
400
200

– 80
– 10

0

550
200
150

1200

600
450

– 80

0

20
—

—
—

100

50
40

900
500
200

600
400
200

900
500
300

300
200
100

– 200

– 70
– 50

275
100

75

600
300
225

– 180

– 50
– 30

1.5

5.0

7.0
No

Limit

200
100

80

1800
1000

400

1200

800
400

1800
1000

600

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

0.9

2.5

3.5

15

Disable, MR, Latch Enable

Rise and Fall Times

Scan Oscillator Frequency

(C1 measured in µF)

— t

1 f

TLH

t

THL

osc

,

5.0
10
15

5.0
10
15

—
—
—

—
—
—

—
—
—

1.5/C1

4.2/C1

7.0/C1

15

5.0

4.0
—

—
—

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ns

ns

ns

ns

ns

ns

ns

ns

ns

MHz

ns

µs

Hz

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4

UNITS CLOCK

UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3

TENS CLOCK

TENS Q0

MC14553B

1000

999

998

997

996

995

994

993

992

991

990

901

900

899

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

17

16

15

14

13

12

11

10

987

6

543

2

1

TENS Q3

HUNDREDS

HUNDREDS Q0
HUNDREDS Q3

DISABLE

OVERFLOW

MASTER

SCAN

OSCILLATOR
DIGIT SELECT 1
DIGIT SELECT 2

DIGIT SELECT 3

(a)
PULSE

GENERATOR

CLOCK

RESET

(DISABLES CLOCK WHEN HIGH)

UNITS

TENS

HUNDREDS

Figure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)

16 V

DD

8V

SS

O.F .
DS
DS
DS

Q3
Q2
Q1
Q0

1

C

2
3

C

LE

DIS

MR

UP AT 80

UP AT 980

UP AT 800

C

L

C

L

C

L

C

L

L

CLOCK

BCD OUT

90%

10%

t

PLH

OVERFLOW

20 ns

t

TLH

10%

20 ns

90%

50%

t

PHL

t

THL

999

1000

50%

1/f

t

t

WL(cl)

cl

PHL

50%

(b)

GENERATOR

1

GENERATOR

2

GENERATOR

3

C

LE

MR

DIS

t

TLH

V

DD

CLOCK

Q3
Q2
Q1
Q0

O.F.
DS

1
2

DS
DS

3

V

SS

C

L

C

L

C

L

C

L

C

L

LATCH
ENABLE

BCD OUT

MASTER RESET

Figure 2. Switching Time Test Circuits and Waveforms

50%

90%

10%

t

su

t

rem

50%

t

, t

PHL

PLH

t

su

50%

t

PHL

50%

t

WH(R)

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5

MC14553B

OPERA TING CHARACTERISTICS

The MC14553B three–digit counter, shown in Figure 3,
consists of three negative edge–triggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits
storage of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time
division multiplexed, providing one BCD number or digit at
a time. Digit select outputs (active low) are provided for
display control. All outputs are TTL compatible.

An on–chip oscillator provides the low frequency
scanning clock which drives the multiplexer output selector .
The frequency of the oscillator can be controlled externally
by a capacitor between pins 3 and 4, or it can be overridden
and driven with an external clock at pin 4. Multiple devices
can be cascaded using the overflow output, which provides
one pulse for every 1000 counts.

LATCH ENABLE

10

CLOCK

12

÷10

UNITS

÷10

TENS

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3

QUAD

LATCH

QUAD

LATCH

PULSE

SHAPER

11
DISABLE
(ACTIVE

HIGH)

C
R

C

R

The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue
operating on input pulses with very slow rise times.
Information present in the counters when the latch input
goes high, will be stored in the latches and will be retained
while the latch input is high, independent of other inputs.
Information can be recovered from the latches after the
counters have been reset if Latch Enable remains high
during the entire reset cycle.

C1

A

SCAN

R

OSCILLATOR

R

SCANNER

MULTIPLEXER

4
3

C1

B

C1

PULSE

GENERATOR

9

Q0

7

Q1

6

Q2

BCD

OUTPUTS

(ACTIVE

HIGH)

C

R

÷10

HUNDREDS

13 14

MR

(ACTIVE HIGH)

Q0
Q1
Q2
Q3

OVERFLOW

QUAD

LATCH

2115

DS

(LSD) DIGIT SELECT (MSD)

Figure 3. Expanded Block Diagram

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6

1DS2DS3

(ACTIVE LOW)

5

Q3

4

C1AC1

MC14553B

9

1011121315

c

a

b

3

14

B

O.F.

A

5

3

d

MC14543B

B

C

DPhLD

2

461

efg

14

MSD

BI

7

RESET

STROBE

10 13

10 13

12

0.001

4

C1AC1

LE MR LE MR

12

CLOCK

MC14553B

CLK

F

µ

3

B

CLK

INPUT

Q3 Q2 Q1 Q0 DS3 DS2 DS1

DIS

11

14

O.F.

MC14553B

Q3 Q2 Q1 Q0 DS3 DS2 DS1

DIS

11

DD

V

56791512

DD

V

56791512

Figure 4. Six–Digit Display

9101112131514

c

a

b

ABCDPhLDBI

532

d

e

MC14543B

4

6

f

1

DD

V

< 10 mA PER SEGMENT)

peak

(I

DISPLAYS ARE LOW CURRENT LEDs

g

LSD

7

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7

P ACKAGE DIMENSIONS

PLASTIC DIP PACKAGE

–A–

916

B

18

F

H

G

D

16 PL

0.25 (0.010) T

C

S

SEATING

–T–

PLANE

K

M

A

MC14553B

PDIP–16

P SUFFIX

CASE 648–08

ISSUE R

J

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

L

M

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES

____

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8

MC14553B

P ACKAGE DIMENSIONS

SOIC–16

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–03

ISSUE B

16 9

M

B

H8X

M

0.25

0.25 B

14X

D

B16X

M

S

A

T

e

A

q

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

E

_

h X 45

81

B

S

A

L

A1

SEATING
PLANE

T

C

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

q

0 7

__

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9

Notes

MC14553B

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10

Notes

MC14553B

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11

MC14553B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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MC14553B/D